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74LVC1G11GM PDF预览

74LVC1G11GM

更新时间: 2024-11-21 11:12:03
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
16页 256K
描述
Single 3-input AND gateProduction

74LVC1G11GM 数据手册

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74LVC1G11  
Single 3-input AND gate  
Rev. 13 — 9 May 2023  
Product data sheet  
1. General description  
The 74LVC1G11 is a single 3-input AND gate. Inputs can be driven from either 3.3 V or 5 V  
devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V  
environments.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
Overvoltage tolerant inputs to 5.5 V  
High noise immunity  
±24 mA output drive (VCC = 3.0 V)  
CMOS low power dissipation  
Direct interface with TTL levels  
IOFF circuitry provides partial Power-down mode operation  
Latch-up performance exceeds 250 mA  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
JESD36 (4.5 V to 5.5 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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