Datasheet > 74LVC1G08GV

74LVC1G08GV

更新时间： 2024-11-21 11:12:23

品牌	Logo	应用领域
安世 - NEXPERIA		PC 光电二极管逻辑集成电路
页数	文件大小	规格书
17页	261K
描述
Single 2-input AND gateProduction

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74LVC1G08GV 数据手册

74LVC1G08

Single 2-input AND gate

Rev. 14 — 24 February 2022

Product data sheet

1. General description

The 74LVC1G08 is a single 2-input AND gate. Inputs can be driven from either 3.3 V or 5 V

devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V

applications.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.

This device is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

2. Features and benefits

•

Wide supply voltage range from 1.65 V to 5.5 V

•

High noise immunity

±24 mA output drive (V_CC= 3.0 V)

CMOS low power dissipation

Direct interface with TTL levels

Overvoltage tolerant inputs to 5.5 V

I_OFFcircuitry provides partial Power-down mode operation

Latch-up performance ≤ 250 mA

Complies with JEDEC standard:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

•

Multiple package options

Specified from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...17

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74LVC1G08GV 替代型号

型号	品牌	替代类型	描述	数据表
1P1G08MDBVREPG4	TI	功能相似	SINGLE 2-INPUT POSITIVE-AND GATE

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