Datasheet > 74LVC16373ADGG,512

74LVC16373ADGG,512

更新时间： 2024-09-09 14:47:07

品牌	Logo	应用领域
恩智浦 - NXP		/
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17页	209K
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74LVC16373ADGG,512 数据手册

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74LVC16373A; 74LVCH16373A

16-bit D-type transparent latch with 5 V tolerant

inputs/outputs; 3-state

Rev. 8 — 6 January 2014

Product data sheet

1. General description

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring

separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state

outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable

(OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices.

When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of

these devices in mixed 3.3 V and 5 V applications.

The device consists of two sections of eight D-type transparent latches with 3-state true

outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the

latches are transparent, that is, the latch outputs change each time its corresponding

D-input changes. The latches store the information that was present at the D-inputs one

set-up time (t_su) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the

contents of the eight latches are available at the outputs. When OE is HIGH, the outputs

go to the high impedance OFF-state. Operation of the OE input does not affect the state of

the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors

to hold unused inputs.

2. Features and benefits

 5 V tolerant inputs/outputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 Multibyte flow-through standard pinout architecture

 Multiple low inductance supply pins for minimum noise and ground bounce

 Direct interface with TTL levels

 All data inputs have bus hold (74LVCH16373A only)

 High-impedance when V_CC= 0 V

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...17

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与74LVC16373ADGG,512相关器件

型号	品牌	获取价格	描述	数据表
74LVC16373ADGG-Q100	NEXPERIA	获取价格	16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
74LVC16373ADGGRG4	TI	获取价格	16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74LVC16373ADGG-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, SOT-362-1,
74LVC16373ADG-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74LVC16373ADGV	NEXPERIA	获取价格	16-bit D-type transparent latch with 5 V tole
74LVC16373ADGV-Q100	NEXPERIA	获取价格	16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
74LVC16373ADGVRE4	TI	获取价格	16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74LVC16373ADGVRG4	TI	获取价格	16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74LVC16373ADL	NXP	获取价格	16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
74LVC16373ADL,112	NXP	获取价格	74LVC(H)16373A - 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

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