Datasheet > 74LVC16373A-Q100

74LVC16373A-Q100

更新时间： 2024-11-12 01:00:55

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
15页	252K
描述
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

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74LVC16373A-Q100 数据手册

74LVC16373A-Q100;

74LVCH16373A-Q100

16-bit D-type transparent latch with 5 V tolerant

inputs/outputs; 3-state

Rev. 3 — 15 February 2019

Product data sheet

1. General description

The 74LVC16373A-Q100 and 74LVCH16373A-Q100 are 16-bit D-type transparent latches

featuring separate D-type inputs with bus hold (74LVCH16373A-Q100 only) for each latch and

3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable

(OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When

disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices

in mixed 3.3 V and 5 V applications.

The device consists of two sections of eight D-type transparent latches with 3-state true outputs.

When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are

transparent, that is, the latch outputs change each time its corresponding D-input changes. The

latches store the information that was present at the D-inputs one set-up time (t_su) preceding the

HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at

the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the

OE input does not affect the state of the latches. Bus hold on the data inputs eliminates the need

for external pull-up resistors to hold unused inputs.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Multibyte flow-through standard pinout architecture

Multiple low inductance supply pins for minimum noise and ground bounce

Direct interface with TTL levels

All data inputs have bus hold (74LVCH16373A-Q100 only)

High-impedance when V_CC= 0 V

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V

12 3 4 5 6 7...15

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与74LVC16373A-Q100相关器件

型号	品牌	获取价格	描述	数据表
74LVC16373DB-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74LVC16373DGGRE4	TI	获取价格	具有三态输出的 16 位透明 D 型锁存器 \| DGG \| 48 \| -40 to 85
74LVC16373PW-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74LVC16374A	NXP	获取价格	16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs 3-State
74LVC16374ABQ	NXP	获取价格	16-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state
74LVC16374ABQ,518	NXP	获取价格	74LVC(H)16374A - 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state QFN 60-Pin
74LVC16374ADGG	NEXPERIA	获取价格	16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-stateProduction
74LVC16374ADGG	NXP	获取价格	16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs 3-State
74LVC16374ADGG,112	NXP	获取价格	74LVC(H)16374A - 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state TSSOP 48-Pi
74LVC16374ADGG,118	NXP	获取价格	74LVC(H)16374A - 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state TSSOP 48-Pi

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