5秒后页面跳转
捷配首页

Datasheet > 74HC193D
74HC193D PDF预览

74HC193D

更新时间： 2024-12-01 11:11:43
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
24页 326K
描述
Presettable synchronous 4-bit binary up/down counterProduction

阅读下载

中文翻译

获取价格

74HC193D 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：SOP,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.57
其他特性：TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK计数方向：BIDIRECTIONAL
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
工作模式：SYNCHRONOUS湿度敏感等级：1
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
传播延迟（tpd）：65 ns座面最大高度：1.75 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30触发器类型：POSITIVE EDGE
宽度：3.9 mm最小 fmax：13 MHz
Base Number Matches：1

74HC193D 数据手册

 浏览型号74HC193D的Datasheet PDF文件第2页浏览型号74HC193D的Datasheet PDF文件第3页浏览型号74HC193D的Datasheet PDF文件第4页浏览型号74HC193D的Datasheet PDF文件第5页浏览型号74HC193D的Datasheet PDF文件第6页浏览型号74HC193D的Datasheet PDF文件第7页 
74HC193; 74HCT193  
Presettable synchronous 4-bit binary up/down counter  
Rev. 7 — 8 September 2021  
Product data sheet  
1. General description  
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down  
clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously  
with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held  
HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will  
count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior.  
The device can be cleared at any time by the asynchronous master reset input (MR); it may also  
be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up  
(TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached  
the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go  
LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,  
the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The  
terminal count outputs can be used as the clock input signals to the next higher order circuit in  
a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be  
fully synchronous, since there is a slight delay time difference added for each stage that is added.  
The counter may be preset by the asynchronous parallel load capability of the circuit. Information  
present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs  
(Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW.  
A HIGH level on the master reset (MR) input will disable the parallel load gates, override both  
clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after  
a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a  
legitimate signal and will be counted. Inputs include clamp diodes. This enables the use of current  
limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
•
Wide supply voltage range from 2.0 to 6.0 V  
•
•
•
•
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Input levels:  
•
•
For 74HC193: CMOS level  
For 74HCT193: TTL level  
•
•
•
•
•
Synchronous reversible 4-bit binary counting  
Asynchronous parallel load  
Asynchronous reset  
Expandable without external logic  
Complies with JEDEC standards:  
•
•
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
•
•
ESD protection:  
•
•
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V.  
Specified from -40 °C to +85 °C and -40 °C to +125 °C.  
 
 
1234567...24

中文翻译

下载PDF

与74HC193D相关器件

型号 品牌 获取价格 描述 数据表
74HC193DB NXP

获取价格

 		Presettable synchronous 4-bit binary up/down counter
74HC193DB-Q100 NXP

获取价格

 		IC BINARY COUNTER, Counter
74HC193DB-Q100 NEXPERIA

获取价格

 		Presettable synchronous 4-bit binary up/down counter
74HC193DB-Q100J NXP

获取价格

 		74HC(T)193-Q100 - Presettable synchronous 4-bit binary up/down counter SSOP1 16-Pin
74HC193DB-T NXP

获取价格

 		IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, S
74HC193D-Q100 NEXPERIA

获取价格

 		Presettable synchronous 4-bit binary up/down counter
74HC193D-Q100J NXP

获取价格

 		74HC(T)193-Q100 - Presettable synchronous 4-bit binary up/down counter SOP 16-Pin
74HC193D-T NXP

获取价格

 		IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, 3
74HC193N NXP

获取价格

 		Presettable synchronous 4-bit binary up/down counter
74HC193N,652 NXP

获取价格

 		74HC(T)193 - Presettable synchronous 4-bit binary up, down counter DIP 16-Pin

与74HC193D相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证