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74HC193PW PDF预览

74HC193PW

更新时间： 2024-11-19 06:31:51
品牌 Logo 应用领域
恩智浦 - NXP 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
29页 151K
描述
Presettable synchronous 4-bit binary up/down counter

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中文翻译

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74HC193PW 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：TSSOP
包装说明：SOT-403-1, TSSOP-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.29其他特性：TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
计数方向：BIDIRECTIONAL系列：HC/UH
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：5 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：13000000 Hz最大I（ol）：0.004 A
工作模式：SYNCHRONOUS湿度敏感等级：1
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2/6 V
传播延迟（tpd）：65 ns认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Counters
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：13 MHz

74HC193PW 数据手册

 浏览型号74HC193PW的Datasheet PDF文件第2页浏览型号74HC193PW的Datasheet PDF文件第3页浏览型号74HC193PW的Datasheet PDF文件第4页浏览型号74HC193PW的Datasheet PDF文件第5页浏览型号74HC193PW的Datasheet PDF文件第6页浏览型号74HC193PW的Datasheet PDF文件第7页 
74HC193; 74HCT193  
Presettable synchronous 4-bit binary up/down counter  
Rev. 03 — 23 May 2007  
Product data sheet  
1. General description  
The 74HC193 and 74HCT193 are high-speed Si-gate CMOS devices and are pin  
compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with  
JEDEC standard no. 7A.  
The 74HC193 and 74HCT193 are 4-bit synchronous binary up/down counters. Separate  
up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state  
synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is  
pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while  
CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at  
any time, or erroneous operation will result. The device can be cleared at any time by the  
asynchronous master reset input (MR); it may also be loaded in parallel by activating the  
asynchronous parallel load input (PL).  
The 74HC193 and 74HCT193 each contain four master-slave JK flip-flops with the  
necessary steering logic to provide the asynchronous reset, load, and synchronous count  
up and count down functions.  
Each flip-flop contains JK feedback from slave to master, such that a LOW-to-HIGH  
transition on the CPD input will decrease the count by one, while a similar transition on the  
CPU input will advance the count by one.  
One clock should be held HIGH while counting with the other, otherwise the circuit will  
either count by twos or not at all, depending on the state of the first flip-flop, which cannot  
toggle as long as either clock input is LOW. Applications requiring reversible operation  
must make the reversing decision while the activating clock is HIGH to avoid erroneous  
counts.  
The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH.  
When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW  
transition of CPU will cause TCU to go LOW.  
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock.  
Likewise, the TCD output will go LOW when the circuit is in the zero state and the  
CPD goes LOW. The terminal count outputs can be used as the clock input signals to the  
next higher order circuit in a multistage counter, since they duplicate the clock waveforms.  
Multistage counters will not be fully synchronous, since there is a slight delay time  
difference added for each stage that is added.  
The counter may be preset by the asynchronous parallel load capability of the circuit.  
Information present on the parallel data inputs (D0 to D3) is loaded into the counter and  
appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when  
the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will  
disable the parallel load gates, override both clock inputs and set all outputs (Q0 to  
1234567...29

中文翻译

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74HC193PW 替代型号

型号 品牌 替代类型 描述 数据表
74HC191PW-T NXP

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