74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the
next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will
be counted.
2. Features
I Synchronous reversible 4-bit binary counting
I Asynchronous parallel load
I Asynchronous reset
I Expandable without external logic
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74HC193D
−40 °C to +125 °C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SOT338-1
74HC193DB
−40 °C to +125 °C SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
74HC193N
−40 °C to +125 °C DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HC193PW
−40 °C to +125 °C TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT193D
−40 °C to +125 °C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SOT338-1
74HCT193DB
−40 °C to +125 °C SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
74HCT193N
−40 °C to +125 °C DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HCT193PW
−40 °C to +125 °C TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
4. Functional diagram
15
D0
1
10
D2
9
D1
D3
PL
TCU
TCD
11
5
PL
11
D0
15
D1
1
D2
10
D3
9
12
13
CPU
CPD
COUNTER
4
CPU
CPD
5
4
12
13
TCU
TCD
MR
14
FLIP-FLOPS
Q0 Q1 Q2
14
3
2
6
7
Q3
MR Q0
Q1
Q2
Q3 001aag409
3
2
6
7
001aag405
Fig 1. Functional diagram
Fig 2. Logic symbol
74HC_HCT193_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 23 May 2007
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