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74HC193DB-Q100 PDF预览

74HC193DB-Q100

更新时间： 2024-11-18 02:56:59
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
29页 776K
描述
Presettable synchronous 4-bit binary up/down counter

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74HC193DB-Q100 技术参数

生命周期：End Of Life包装说明：SSOP,
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.59Is Samacsys：N
计数方向：BIDIRECTIONAL系列：HC/UH
JESD-30 代码：R-PDSO-G16长度：6.2 mm
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
传播延迟（tpd）：325 ns筛选级别：AEC-Q100
座面最大高度：2 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：5.3 mm
最小 fmax：15 MHzBase Number Matches：1

74HC193DB-Q100 数据手册

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74HC193-Q100; 74HCT193-Q100  
Presettable synchronous 4-bit binary up/down counter  
Rev. 1 — 12 July 2013  
Product data sheet  
1. General description  
The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter.  
Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs  
change state synchronously with the LOW-to-HIGH transition of either clock input. If the  
CPU clock is pulsed while CPD is held HIGH, the device counts up. If the CPD clock is  
pulsed while CPU is held HIGH, the device counts down. Only one clock input can be held  
HIGH at any time to guarantee predictable behavior. The device can be cleared at any  
time by the asynchronous master reset input (MR). It may also be loaded in parallel by  
activating the asynchronous parallel load input (PL). The terminal count up (TCU) and  
terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the  
maximum count state of 15, the next HIGH-to-LOW transition of CPU causes TCU to go  
LOW. TCU remains LOW until CPU goes HIGH again, duplicating the count up clock.  
Likewise, the TCD output goes LOW when the circuit is in the zero state and the CPD  
goes LOW. The terminal count outputs duplicate the clock waveforms and can be used as  
the clock input signals to the next higher-order circuit in a multistage counter. Multistage  
counters are not fully synchronous, since there is a slight delay time difference added for  
each stage that is added. The counter may be preset by the asynchronous parallel load  
capability of the circuit. Information on the parallel data inputs (D0 to D3), is loaded into  
the counter. This information appears on the outputs (Q0 to Q3) regardless of the  
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on  
the master reset (MR) input disables the parallel load gates. It overrides both clock inputs  
and sets all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a  
reset or load operation, the next LOW-to-HIGH transition of that clock is interpreted as a  
legitimate signal and it is counted. Inputs include clamp diodes that enable the use of  
current limiting resistors to interface inputs to voltages in excess of VCC  
.
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Input levels:  
For 74HC193-Q100: CMOS level  
For 74HCT193-Q100: TTL level  
Synchronous reversible 4-bit binary counting  
Asynchronous parallel load  
Asynchronous reset  
Expandable without external logic  
Complies with JEDEC standard no. 7A  
1234567...29

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