Datasheet > 74HC193DB-Q100J

74HC193DB-Q100J

更新时间： 2024-02-15 13:10:07

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
29页	190K
描述
74HC(T)193-Q100 - Presettable synchronous 4-bit binary up/down counter SSOP1 16-Pin

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74HC193DB-Q100J 技术参数

生命周期：	Active	零件包装代码：	SSOP1
包装说明：	SSOP,	针数：	16
Reach Compliance Code：	compliant	风险等级：	5.66
计数方向：	BIDIRECTIONAL	系列：	HC/UH
JESD-30 代码：	R-PDSO-G16	长度：	6.2 mm
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
工作模式：	SYNCHRONOUS	位数：	4
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
传播延迟（tpd）：	325 ns	筛选级别：	AEC-Q100
座面最大高度：	2 mm	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
触发器类型：	POSITIVE EDGE	宽度：	5.3 mm
最小 fmax：	15 MHz	Base Number Matches：	1

74HC193DB-Q100J 数据手册

74HC193-Q100; 74HCT193-Q100

Presettable synchronous 4-bit binary up/down counter

Rev. 1 — 12 July 2013

Product data sheet

1. General description

The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter.

Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs

change state synchronously with the LOW-to-HIGH transition of either clock input. If the

CPU clock is pulsed while CPD is held HIGH, the device counts up. If the CPD clock is

pulsed while CPU is held HIGH, the device counts down. Only one clock input can be held

HIGH at any time to guarantee predictable behavior. The device can be cleared at any

time by the asynchronous master reset input (MR). It may also be loaded in parallel by

activating the asynchronous parallel load input (PL). The terminal count up (TCU) and

terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the

maximum count state of 15, the next HIGH-to-LOW transition of CPU causes TCU to go

LOW. TCU remains LOW until CPU goes HIGH again, duplicating the count up clock.

Likewise, the TCD output goes LOW when the circuit is in the zero state and the CPD

goes LOW. The terminal count outputs duplicate the clock waveforms and can be used as

the clock input signals to the next higher-order circuit in a multistage counter. Multistage

counters are not fully synchronous, since there is a slight delay time difference added for

each stage that is added. The counter may be preset by the asynchronous parallel load

capability of the circuit. Information on the parallel data inputs (D0 to D3), is loaded into

the counter. This information appears on the outputs (Q0 to Q3) regardless of the

conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on

the master reset (MR) input disables the parallel load gates. It overrides both clock inputs

and sets all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a

reset or load operation, the next LOW-to-HIGH transition of that clock is interpreted as a

legitimate signal and it is counted. Inputs include clamp diodes that enable the use of

current limiting resistors to interface inputs to voltages in excess of V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Input levels:

 For 74HC193-Q100: CMOS level

 For 74HCT193-Q100: TTL level

 Synchronous reversible 4-bit binary counting

 Asynchronous parallel load

 Asynchronous reset

 Expandable without external logic

 Complies with JEDEC standard no. 7A

12 3 4 5 6 7...29

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与74HC193DB-Q100J相关器件

型号	品牌	描述	获取价格	数据表
74HC193DB-T	NXP	IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, S	获取价格
74HC193D-Q100	NEXPERIA	Presettable synchronous 4-bit binary up/down counter	获取价格
74HC193D-Q100J	NXP	74HC(T)193-Q100 - Presettable synchronous 4-bit binary up/down counter SOP 16-Pin	获取价格
74HC193D-T	NXP	IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, 3	获取价格
74HC193N	NXP	Presettable synchronous 4-bit binary up/down counter	获取价格
74HC193N,652	NXP	74HC(T)193 - Presettable synchronous 4-bit binary up, down counter DIP 16-Pin	获取价格

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