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74HC173PW PDF预览

74HC173PW

更新时间: 2024-11-02 11:12:43
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
17页 270K
描述
Quad D-type flip-flop; positive-edge trigger; 3-stateProduction

74HC173PW 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.62
其他特性:WITH HOLD MODE系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm逻辑集成电路类型:D FLIP-FLOP
湿度敏感等级:1位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):53 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:60 MHzBase Number Matches:1

74HC173PW 数据手册

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74HC173; 74HCT173  
Quad D-type flip-flop; positive-edge trigger; 3-state  
Rev. 4 — 25 January 2021  
Product data sheet  
1. General description  
The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features  
clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs.  
When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn  
inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition.  
A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their  
previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW  
independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to  
assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the  
state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors  
to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Complies with JEDEC standard no. 7A  
Input levels:  
For 74HC173: CMOS level  
For 74HCT173: TTL level  
Gated input enable for hold (do nothing) mode  
Gated output enable control mode  
Edge-triggered D-type register  
Asynchronous master reset  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number Package  
Temperature range Name  
Description  
Version  
74HC173D  
-40 °C to +125 °C  
SO16  
plastic small outline package; 16 leads;  
body width 3.9 mm  
SOT109-1  
74HCT173D  
74HC173PW  
-40 °C to +125 °C  
TSSOP16  
plastic thin shrink small outline package; 16 leads;  
body width 4.4 mm  
SOT403-1  
 
 
 

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