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74HC175D-Q100 PDF预览

74HC175D-Q100

更新时间: 2024-11-19 01:18:47
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
18页 747K
描述
Quad D-type flip-flop with reset; positive-edge trigger

74HC175D-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP-16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.67
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
逻辑集成电路类型:D FLIP-FLOP湿度敏感等级:1
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260传播延迟(tpd):265 ns
筛选级别:AEC-Q100座面最大高度:1.75 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:24 MHz

74HC175D-Q100 数据手册

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74HC175-Q100; 74HCT175-Q100  
Quad D-type flip-flop with reset; positive-edge trigger  
Rev. 1 — 19 May 2014  
Product data sheet  
1. General description  
The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops  
with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and  
master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that  
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is  
stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and  
outputs to be reset LOW.  
The device is useful for applications where both the true and complement outputs are  
required and the clock and master reset are common to all storage elements.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Input levels:  
For 74HC175-Q100: CMOS level  
For 74HCT175-Q100: TTL level  
Four edge-triggered D-type flip-flops  
Asynchronous master reset  
Complies with JEDEC standard no. 7A  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  

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