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74HC175PW PDF预览

74HC175PW

更新时间: 2023-09-03 20:31:09
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
16页 257K
描述
Quad D-type flip-flop with reset; positive-edge triggerProduction

74HC175PW 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.03系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:24000000 Hz
最大I(ol):0.004 A湿度敏感等级:1
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):265 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:24 MHzBase Number Matches:1

74HC175PW 数据手册

 浏览型号74HC175PW的Datasheet PDF文件第2页浏览型号74HC175PW的Datasheet PDF文件第3页浏览型号74HC175PW的Datasheet PDF文件第4页浏览型号74HC175PW的Datasheet PDF文件第5页浏览型号74HC175PW的Datasheet PDF文件第6页浏览型号74HC175PW的Datasheet PDF文件第7页 
74HC175; 74HCT175  
Quad D-type flip-flop with reset; positive-edge trigger  
Rev. 6 — 4 February 2021  
Product data sheet  
1. General description  
The 74HC175; 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data  
inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and master reset  
(MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold  
time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear  
at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include  
clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in  
excess of VCC  
.
2. Features and benefits  
Input levels:  
For 74HC175: CMOS level  
For 74HCT175: TTL level  
Four edge-triggered D-type flip-flops  
Asynchronous master reset  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C.  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC175D  
-40 °C to +125 °C  
-40 °C to +125 °C  
SO16  
plastic small outline package; 16 leads;  
body width 3.9 mm  
SOT109-1  
74HCT175D  
74HC175PW  
74HCT175PW  
TSSOP16  
plastic thin shrink small outline package; 16 leads;  
body width 4.4 mm  
SOT403-1  
 
 
 

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