Datasheet > 74HC175-Q100

74HC175-Q100

更新时间： 2024-11-03 01:18:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
18页	747K
描述
Quad D-type flip-flop with reset; positive-edge trigger

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74HC175-Q100 数据手册

74HC175-Q100; 74HCT175-Q100

Quad D-type flip-flop with reset; positive-edge trigger

Rev. 1 — 19 May 2014

Product data sheet

1. General description

The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops

with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and

master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that

meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is

stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and

outputs to be reset LOW.

The device is useful for applications where both the true and complement outputs are

required and the clock and master reset are common to all storage elements.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Input levels:

 For 74HC175-Q100: CMOS level

 For 74HCT175-Q100: TTL level

 Four edge-triggered D-type flip-flops

 Asynchronous master reset

 Complies with JEDEC standard no. 7A

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

12 3 4 5 6 7...18

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