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74HC175D PDF预览

74HC175D

更新时间: 2024-11-19 11:12:35
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
16页 257K
描述
Quad D-type flip-flop with reset; positive-edge triggerProduction

74HC175D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.31
Samacsys Description:74HC175D, D Type Flip Flop HC, 2 to 6V 16-Pin SOIC系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm逻辑集成电路类型:D FLIP-FLOP
湿度敏感等级:1位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):265 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:24 MHz

74HC175D 数据手册

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74HC175; 74HCT175  
Quad D-type flip-flop with reset; positive-edge trigger  
Rev. 6 — 4 February 2021  
Product data sheet  
1. General description  
The 74HC175; 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data  
inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and master reset  
(MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold  
time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear  
at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include  
clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in  
excess of VCC  
.
2. Features and benefits  
Input levels:  
For 74HC175: CMOS level  
For 74HCT175: TTL level  
Four edge-triggered D-type flip-flops  
Asynchronous master reset  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C.  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC175D  
-40 °C to +125 °C  
-40 °C to +125 °C  
SO16  
plastic small outline package; 16 leads;  
body width 3.9 mm  
SOT109-1  
74HCT175D  
74HC175PW  
74HCT175PW  
TSSOP16  
plastic thin shrink small outline package; 16 leads;  
body width 4.4 mm  
SOT403-1  
 
 
 

74HC175D 替代型号

型号 品牌 替代类型 描述 数据表
74HC175D,652 NXP

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