Datasheet > 74AUP2G08_11

74AUP2G08_11

更新时间： 2024-11-18 08:03:15

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74AUP2G08_11 数据手册

74AUP2G08

Low-power dual 2-input AND gate

Rev. 5 — 1 December 2011

Product data sheet

1. General description

The 74AUP2G08 provides the dual 2-input AND function.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits

 Wide supply voltage range from 0.8 V to 3.6 V

 High noise immunity

 Complies with JEDEC standards:

 JESD8-12 (0.8 V to 1.3 V)

 JESD8-11 (0.9 V to 1.65 V)

 JESD8-7 (1.2 V to 1.95 V)

 JESD8-5 (1.8 V to 2.7 V)

 JESD8-B (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Low static power consumption; I_CC= 0.9 A (maximum)

 Latch-up performance exceeds 100 mA per JESD78 Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V_CC

 I_OFFcircuitry provides partial power-down mode operation

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...21

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型号	品牌	获取价格	描述	数据表
74AUP2G08DC	NXP	获取价格	Low-power dual 2-input AND gate
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74AUP2G08GD	NXP	获取价格	Low-power dual 2-input AND gate
74AUP2G08GD,125	NXP	获取价格	74AUP2G08 - Low-power dual 2-input AND gate SON 8-Pin
74AUP2G08GF	NXP	获取价格	Low-power dual 2-input AND gate
74AUP2G08GF,115	NXP	获取价格	74AUP2G08 - Low-power dual 2-input AND gate SON 8-Pin
74AUP2G08GM	NXP	获取价格	Low-power dual 2-input AND gate
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74AUP2G08GM-G	NXP	获取价格	IC AUP/ULP/V SERIES, DUAL 2-INPUT AND GATE, PQCC8, 1.60 X 1.60 MM, 0.50 MM HEIGHT, PLASTIC