Datasheet > 74AUP2G08DC-Q100

74AUP2G08DC-Q100

更新时间： 2024-11-19 15:19:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
13页	217K
描述
Low-power dual 2-input AND gateProduction

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74AUP2G08DC-Q100 数据手册

74AUP2G08-Q100

Low-power dual 2-input AND gate

Rev. 1 — 16 October 2023

Product data sheet

1. General description

The 74AUP2G08 is a dual 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit

tolerant of slower input rise and fall times. This device ensures very low static and dynamic power

consumption across the entire V_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 0.8 V to 3.6 V

High noise immunity

CMOS low power dissipation

Low static power consumption; I_CC= 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD78 Class II

Overvoltage tolerant inputs to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial Power-down mode operation

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Complies with JEDEC standards:

•

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

•

ESD protection:

•

HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

12 3 4 5 6 7...13

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