Datasheet > 逻辑 > 总线驱动器/收发器> 74AUP2G125DC

74AUP2G125DC

更新时间： 2024-11-16 04:00:55

品牌	Logo	应用领域
恩智浦 - NXP		驱动器
页数	文件大小	规格书
19页	102K
描述
Low-power dual buffer/line driver; 3-state

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AUP2G125DC 数据手册

74AUP2G125

Low-power dual buffer/line driver; 3-state

Rev. 02 — 19 April 2007

Product data sheet

1. General description

The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output.

The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE

causes the output to assume a high-impedance OFF-state. This device has the

input-disable feature, which allows ﬂoating input signals. The inputs are disabled when the

output enable input nOE) is HIGH.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V. This device ensures a very low

static and dynamic power consumption across the entire V_CCrange from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial Power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

2. Features

■ Wide supply voltage range from 0.8 V to 3.6 V

■ High noise immunity

■ Complies with JEDEC standards:

◆ JESD8-12 (0.8 V to 1.3 V)

◆ JESD8-11 (0.9 V to 1.65 V)

◆ JESD8-7 (1.2 V to 1.95 V)

◆ JESD8-5 (1.8 V to 2.7 V)

◆ JESD8-B (2.7 V to 3.6 V)

■ ESD protection:

◆ HBM JESD22-A114-D Class 3A exceeds 5000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101-C exceeds 1000 V

■ Low static power consumption; I_CC= 0.9 µA (maximum)

■ Latch-up performance exceeds 100 mA per JESD 78 Class II

■ Inputs accept voltages up to 3.6 V

■ Low noise overshoot and undershoot < 10 % of V_CC

■ Input-disable feature allows ﬂoating input conditions

■ I_OFFcircuitry provides partial Power-down mode operation

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...19

中文翻译

下载PDF

与74AUP2G125DC相关器件

型号	品牌	获取价格	描述	数据表
74AUP2G125DC,125	NXP	获取价格	74AUP2G125 - Low-power dual buffer/line driver; 3-state SSOP 8-Pin
74AUP2G125DC-G	NXP	获取价格	Low-power dual buffer/line driver; 3-state
74AUP2G125GD	NXP	获取价格	Low-power dual buffer/line driver; 3-state
74AUP2G125GD,125	NXP	获取价格	74AUP2G125 - Low-power dual buffer/line driver; 3-state SON 8-Pin
74AUP2G125GF	NXP	获取价格	Low-power dual buffer/line driver; 3-state
74AUP2G125GF,115	NXP	获取价格	74AUP2G125 - Low-power dual buffer/line driver; 3-state SON 8-Pin
74AUP2G125GM	NXP	获取价格	Low-power dual buffer/line driver; 3-state
74AUP2G125GM,125	NXP	获取价格	74AUP2G125 - Low-power dual buffer/line driver; 3-state QFN 8-Pin
74AUP2G125GM-G	NXP	获取价格	IC,BUFFER/DRIVER,DUAL,1-BIT,CMOS,LLCC,8PIN,PLASTIC
74AUP2G125GN	NXP	获取价格	Low-power dual buffer/line driver; 3-state