Datasheet > 74AUP2G02DC

74AUP2G02DC

更新时间： 2023-09-03 20:29:10

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
17页	264K
描述
Low-power dual 2-input NOR gateProduction

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数据手册

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74AUP2G02DC 数据手册

Nexperia

74AUP2G02

Low-power dual 2-input NOR gate

4. Marking

Table 2. Marking codes

Type number

Marking code[1]

74AUP2G02DC

74AUP2G02GT

74AUP2G02GF

74AUP2G02GN

74AUP2G02GS

p02

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

≥ 1

001aah877

001aah879

mna105

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

Fig. 3. Logic diagram

6. Pinning information

6.1. Pinning

74AUP2G02

GND

001aae472

Transparent top view

GND

001aae412

Fig. 5. Pin configuration SOT833-1, SOT1089, SOT1116

and SOT1203 (XSON8)

Fig. 4. Pin configuration SOT765-1 (VSSOP8)

74AUP2G02

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 27 July 2021

2 / 17

123 4 5 6 7...17

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