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74ALVCH16841DGGRE4 PDF预览

74ALVCH16841DGGRE4

更新时间： 2024-11-09 14:48:55
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 341K
描述
20-Bit Bus-Interface D-Type Latch With 3-State Outputs 56-TSSOP -40 to 85

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74ALVCH16841DGGRE4 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：GREEN, PLASTIC, TSSOP-56
针数：56Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.33
Is Samacsys：N系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：14 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：10
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：3.9 ns
传播延迟（tpd）：5.6 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

74ALVCH16841DGGRE4 数据手册

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SN74ALVCH16841  
20-BIT BUS-INTERFACE D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES043E–JULY 1995–REVISED SEPTEMBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
•
•
Member of the Texas Instruments Widebus™  
Family  
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56  
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EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
2
3
ESD Protection Exceeds 2000 V Per  
4
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
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6
•
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
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V
CC  
V
CC  
8
1D5  
1D6  
1D7  
GND  
1D8  
1D9  
1D10  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
1Q5  
1Q6  
1Q7  
GND  
1Q8  
1Q9  
1Q10  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
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Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
DESCRIPTION  
This 20-bit bus-interface D-type latch is designed for  
1.65-V to 3.6-V VCC operation.  
The SN74ALVCH16841 features 3-state outputs  
designed specifically for driving highly capacitive or  
relatively low-impedance loads. This device is  
particularly suitable for implementing buffer registers,  
unidirectional bus drivers, and working registers.  
V
CC  
V
CC  
2D7  
2D8  
GND  
2D9  
2D10  
2LE  
2Q7  
2Q8  
The SN74ALVCH16841 can be used as two 10-bit  
latches or one 20-bit latch. The 20 latches are  
transparent D-type latches. The device has  
noninverting data (D) inputs and provides true data at  
its outputs. While the latch-enable (1LE or 2LE) input  
is high, the Q outputs of the corresponding 10-bit  
latch follow the D inputs. When LE is taken low, the Q  
outputs are latched at the levels set up at the D  
inputs.  
GND  
2Q9  
2Q10  
2OE  
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch  
in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state,  
the outputs neither load nor drive the bus lines significantly.  
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16841 is characterized for operation from -40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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74ALVCH16841DGGRE4 替代型号

型号 品牌 替代类型 描述 数据表
74ALVCH16841DGGRG4 TI

完全替代

 ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
SN74ALVCH16841DGGR TI

完全替代

 20-Bit Bus-Interface D-Type Latch With 3-State Outputs 56-TSSOP -40 to 85
SN74ALVCH162841GR TI

类似代替

 具有三态输出的 9 位总线接口 D 类锁存器 | DGG | 56 | -40 to 85

与74ALVCH16841DGGRE4相关器件

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74ALVCH16841DGGRG4 TI

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 		ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
74ALVCH16841DGG-T NXP

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 		暂无描述
74ALVCH16841DGGY NXP

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 		74ALVCH16841 - 20-bit bus interface D-type latch (3-State) TSSOP 56-Pin
74ALVCH16841DL NXP

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 		20-bit bus interface D-type latch (3-State)
74ALVCH16841DLG4 TI

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 		20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
74ALVCH16841DLRG4 TI

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 		ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SS
74ALVCH16843 NXP

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 		18-bit bus-interface D-type latch 3-State
74ALVCH16843DGG NXP

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 		18-bit bus-interface D-type latch 3-State
74ALVCH16843DGG NEXPERIA

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 		18-bit bus-interface D-type latch; 3-stateProduction
74ALVCH16843DGG-T PHILIPS

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 		D Latch, 2-Func, 9-Bit, CMOS, PDSO56

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