5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> 74ALVCH16903DLRG4
74ALVCH16903DLRG4 PDF预览

74ALVCH16903DLRG4

更新时间： 2024-11-18 05:05:51
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
16页 221K
描述
3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

74ALVCH16903DLRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.73Is Samacsys：N
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
长度：18.415 mm逻辑集成电路类型：BUS DRIVER
位数：12功能数量：1
端口数量：2端子数量：56
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V传播延迟（tpd）：6.1 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.49 mm
Base Number Matches：1

74ALVCH16903DLRG4 数据手册

 浏览型号74ALVCH16903DLRG4的Datasheet PDF文件第2页浏览型号74ALVCH16903DLRG4的Datasheet PDF文件第3页浏览型号74ALVCH16903DLRG4的Datasheet PDF文件第4页浏览型号74ALVCH16903DLRG4的Datasheet PDF文件第5页浏览型号74ALVCH16903DLRG4的Datasheet PDF文件第6页浏览型号74ALVCH16903DLRG4的Datasheet PDF文件第7页 
SN74ALVCH16903  
3.3-V 12-BIT UNIVERSAL BUS DRIVER  
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS  
www.ti.com  
SCES095D–MARCH 1997–REVISED SEPTEMBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
•
Member of the Texas Instruments Widebus™  
(TOP VIEW)  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
CLK  
OE  
1Y1  
1Y2  
GND  
2Y1  
2Y2  
•
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
2
1A  
3
11A/YERREN  
GND  
11Y1  
•
•
Checks Parity  
4
Able to Cascade With a Second  
SN74ALVCH16903  
5
6
11Y2  
•
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
7
V
CC  
V
CC  
8
2A  
3Y1  
3Y2  
4Y1  
GND  
4Y2  
5Y1  
5Y2  
6Y1  
6Y2  
7Y1  
GND  
7Y2  
8Y1  
8Y2  
9
3A  
4A  
•
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
12A  
12Y1  
12Y2  
5A  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
6A  
7A  
GND  
APAR  
8A  
DESCRIPTION  
This 12-bit universal bus driver is designed for 2.3-V  
to 3.6-V VCC operation.  
YERR  
V
CC  
V
CC  
The SN74ALVCH16903 has dual outputs and can  
operate as a buffer or an edge-triggered register. In  
both modes, parity is checked on APAR, which  
arrives one cycle after the data to which it applies.  
The YERR output, which is produced one cycle after  
APAR, is open drain.  
9A  
MODE  
GND  
9Y1  
9Y2  
GND  
10A  
10Y1  
PARI/O  
CLKEN  
10Y2  
PAROE  
MODE selects one of the two data paths. When  
MODE is low, the device operates as an  
edge-triggered register. On the positive transition of  
the clock (CLK) input and when the clock-enable  
(CLKEN) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition of  
CLK and when CLKEN is high, only data set up at the 9A–12A inputs is stored in their internal registers. When  
MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs.  
11A/YERREN serves a dual purpose; it acts as a normal data bit and also enables YERR data to be clocked into  
the YERR output register.  
When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output  
(PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and  
PAROE is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When used  
in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903.  
A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state  
(high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor  
drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
OE does not affect the internal operation of the device. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...16

中文翻译

下载PDF

与74ALVCH16903DLRG4相关器件

型号 品牌 获取价格 描述 数据表
74ALVCH16903PF IDT

获取价格

 		TVSOP-56, Tube
74ALVCH16903PF8 IDT

获取价格

 		TVSOP-56, Reel
74ALVCH16903PV8 IDT

获取价格

 		SSOP-56, Reel
74ALVCH16952 NXP

获取价格

 		16-bit registered transceiver 3-State
74ALVCH16952DG NXP

获取价格

 		IC ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSS
74ALVCH16952DGG NXP

获取价格

 		16-bit registered transceiver 3-State
74ALVCH16952DGG NEXPERIA

获取价格

 		16-bit registered transceiver; 3-stateProduction
74ALVCH16952DGG:11 NXP

获取价格

 		74ALVCH16952 - 16-bit registered transceiver (3-State) TSSOP 56-Pin
74ALVCH16952DGGRG4 TI

获取价格

 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC,
74ALVCH16952DGG-T NXP

获取价格

 		IC ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLA

与74ALVCH16903DLRG4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证