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74ALVCH16952DGG PDF预览

74ALVCH16952DGG

更新时间: 2024-09-17 11:13:31
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
14页 191K
描述
16-bit registered transceiver; 3-stateProduction

74ALVCH16952DGG 数据手册

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74ALVCH16952  
16-bit registered transceiver; 3-state  
Rev. 3 — 9 January 2018  
Product data sheet  
1 General description  
The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting  
registered transceiver. Two 8-bit back to back registers store data flowing in both  
directions between two bidirectional buses. Data applied to the inputs is entered and  
stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock  
enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but  
is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow  
from A inputs to B outputs is the same as for B inputs to A outputs.  
2 Features and benefits  
CMOS low-power consumption  
Multibyte flow-through pinout architecture  
Low inductance, multiple center power and ground pins for minimum noise and ground  
bounce  
Direct interface with TTL levels  
Output drive capability 50 Ω transmission lines at 85 °C  
Complies with JEDEC standard JESD8-B  
3 Ordering information  
Table 1.ꢀOrdering information  
Type number  
Package  
Temperature range  
Name  
Description  
Version  
74ALVCH16952DGG -40 °C to +85 °C  
TSSOP56  
plastic thin shrink small outline package;  
56 leads; body width 6.1 mm  
SOT364-1  
 
 
 

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