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74ALVCH16952DLRG4 PDF预览

74ALVCH16952DLRG4

更新时间： 2024-11-21 14:47:39
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
17页 363K
描述
16-Bit Registered Transceiver With 3-State Outputs 56-SSOP -40 to 85

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74ALVCH16952DLRG4 技术参数

是否无铅：含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：compliant风险等级：5.49
Is Samacsys：N其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.415 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：4.6 ns
认证状态：Not Qualified座面最大高度：2.79 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.49 mm
Base Number Matches：1

74ALVCH16952DLRG4 数据手册

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SN74ALVCH16952  
16-BIT REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES011E–JULY 1995–REVISED SEPTEMBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
•
•
Member of the Texas Instruments Widebus™  
Family  
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56  
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EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1OEAB  
1CLKAB  
1CLKENAB  
GND  
1OEBA  
1CLKBA  
1CLKENBA  
GND  
2
3
ESD Protection Exceeds 2000 V Per  
4
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
5
1A1  
1B1  
6
1A2  
1B2  
•
•
•
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
7
V
CC  
V
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
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Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
DESCRIPTION  
This 16-bit registered transceiver is designed for  
1.65-V to 3.6-V VCC operation.  
The SN74ALVCH16952 contains two sets of D-type  
flip-flops for temporary storage of data flowing in  
either direction. This device can be used as two 8-bit  
transceivers or one 16-bit transceiver. Data on the A  
or B bus is stored in the registers on the low-to-high  
transition of the clock (CLKAB or CLKBA) input,  
provided that the clock-enable (CLKENAB or  
CLKENBA) input is low. Taking the output-enable  
(OEAB or OEBA) input low accesses the data on  
either port.  
V
CC  
V
CC  
2A7  
2A8  
2B7  
2B8  
GND  
GND  
2CLKENAB  
2CLKAB  
2OEAB  
2CLKENBA  
2CLKBA  
2OEBA  
To ensure the high-impedance state during power up  
or power down, OE should be tied to VCC through a  
pullup resistor; the minimum value of the resistor is  
determined by the current-sinking capability of the  
driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16952 is characterized for operation from -40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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中文翻译

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74ALVCH16952DLRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH16952DLR TI

完全替代

 16-Bit Registered Transceiver With 3-State Outputs 56-SSOP -40 to 85
SN74ALVCH16952DGGR TI

完全替代

 16-Bit Registered Transceiver With 3-State Outputs 56-TSSOP -40 to 85
SN74ALVCH16952DL TI

完全替代

 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

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