Datasheet > 74ALVCH16903PF8

74ALVCH16903PF8

更新时间： 2024-11-22 05:16:35

品牌	Logo	应用领域
艾迪悌 - IDT		电视
页数	文件大小	规格书
13页	133K
描述
TVSOP-56, Reel

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74ALVCH16903PF8 数据手册

IDT74ALVCH16903

3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 12-BIT UNIVERSAL

IDT74ALVCH16903

BUS DRIVER WITH PARITY

CHECKER, DUAL 3-STATE

OUTPUTS AND BUS-HOLD

DESCRIPTION:

FEATURES:

This 12-bit universal bus driver is built using advanced dual metal CMOS

technology. This device has dual outputs and can operate as a buffer or an

edge-triggered register. In both modes, parity is checked on APAR, which

arrivesonecycleafterthedatatowhichitapplies.TheYERRoutput,whichis

produced one cycle after APAR, is open drain.

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• VCC = 2.5V ± 0.2V

• CMOS power levels (0.4μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

MODE selects one of the two data paths. When MODE is low, the device

operatesasanedge-triggeredregister.Onthepositivetransitionoftheclock

(CLK)inputandwhentheclock-enable(CLKEN)inputislow,datasetupatthe

Ainputsisstoredintheinternalregisters.OnthepositivetransitionofCLKand

when CLKEN is high, only data setup at the 9A-12A inputs is stored in their

internalregisters.WhenMODEishigh,thedeviceoperatesasabufferanddata

attheAinputspassesdirectlytotheoutputs.The11A/YERREN servesadual

purpose;itactsasanormaldatabitandalsoenablesYERRdatatobeclocked

intotheYERRoutputregister.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

Whenusedasasingledevice,parityoutputenable(PAROE)mustbetied

high;whenparityinput/output(PARI/O)islow,evenparityisselectedandwhen

PARI/Oishigh,oddparityisselected.WhenusedinpairsandPAROEislow,

theparitysumisoutputonPARI/OforcascadingtothesecondALVCH16903.

WhenusedinpairsandPAROEishigh,PARI/Oacceptsapartialparitysum

fromthefirstALVCH16903.

Abufferedoutput-enable(OE)inputcanbeusedtoplacethe24outputsand

YERRineitheranormallogicstate(highorlowlogiclevels)orahigh-impedance

state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebuslines

significantly. The high-impedance state and increased drive provide the

capabilitytodrivebuslineswithoutneedforinterfaceorpullupcomponents.

The ALVCH16903 has been designed with a ±24mA output driver. This

driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed

performance.

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

Symbol

Description

Max

Unit

(2)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +4.6

(3)

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC+0.5

(Outputs Only)

TSTG

IOUT

IIK

Storage Temperature

DC Output Current

–65 to +150

–50 to +50

±50

° C

Continuous Clamp Current,

VI < 0 or VI > VCC

IOK

Continuous Clamp Current, VO < 0

–50

ICC

ISS

Continuous Current through each

VCC or GND

±100

The ALVCH16903 has “bus-hold” which retains the inputs’ last state

whenevertheinputbusgoestoahigh-impedance.Thispreventsfloatinginputs

andeliminatestheneedforpull-up/downresistors.

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. V^CCterminals.

3. This value is limited to 4.6V maximum.

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

COUT

NOTE:

1. As applicable to the device type.

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JUNE 2006

DSC-4911/4

12 3 4 5 6 7...13

中文翻译

下载PDF

与74ALVCH16903PF8相关器件

型号	品牌	获取价格	描述	数据表
74ALVCH16903PV8	IDT	获取价格	SSOP-56, Reel
74ALVCH16952	NXP	获取价格	16-bit registered transceiver 3-State
74ALVCH16952DG	NXP	获取价格	IC ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSS
74ALVCH16952DGG	NXP	获取价格	16-bit registered transceiver 3-State
74ALVCH16952DGG	NEXPERIA	获取价格	16-bit registered transceiver; 3-stateProduction
74ALVCH16952DGG:11	NXP	获取价格	74ALVCH16952 - 16-bit registered transceiver (3-State) TSSOP 56-Pin
74ALVCH16952DGGRG4	TI	获取价格	ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC,
74ALVCH16952DGG-T	NXP	获取价格	IC ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLA
74ALVCH16952DG-T	NXP	获取价格	IC ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSS
74ALVCH16952DL	ETC	获取价格	Dual 8-bit Bus Transceiver

与74ALVCH16903PF8相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

27
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

19
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

49
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

47

产品中心

服务支持

精选活动

关于我们

帮助中心

74ALVCH16903PF8

74ALVCH16903PF8 数据手册

与74ALVCH16903PF8相关器件

与74ALVCH16903PF8相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74ALVCH16903PF8

74ALVCH16903PF8 数据手册

与74ALVCH16903PF8相关器件

与74ALVCH16903PF8相关文章

您还可以找

您在本页遇到什么问题？