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74ALVCH16646DGVRE4 PDF预览

74ALVCH16646DGVRE4

更新时间： 2024-09-16 15:31:23
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器电视
页数 文件大小 规格书
18页 381K
描述
ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TVSOP-56

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74ALVCH16646DGVRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：TSSOP, TSSOP56,.25,16针数：56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.67其他特性：WITH DIRECTION CONTROL
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：11.3 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.25,16
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：3.9 ns
传播延迟（tpd）：5.6 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

74ALVCH16646DGVRE4 数据手册

 浏览型号74ALVCH16646DGVRE4的Datasheet PDF文件第2页浏览型号74ALVCH16646DGVRE4的Datasheet PDF文件第3页浏览型号74ALVCH16646DGVRE4的Datasheet PDF文件第4页浏览型号74ALVCH16646DGVRE4的Datasheet PDF文件第5页浏览型号74ALVCH16646DGVRE4的Datasheet PDF文件第6页浏览型号74ALVCH16646DGVRE4的Datasheet PDF文件第7页 
SN74ALVCH16646  
16-BIT BUS TRANSCEIVER AND REGISTER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES032F–JULY 1995–REVISED SEPTEMBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
•
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1DIR  
1CLKAB  
1SAB  
GND  
1OE  
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
2
1CLKBA  
1SBA  
GND  
1B1  
3
ESD Protection Exceeds 2000 V Per  
4
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
5
1A1  
6
1A2  
1B2  
•
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
7
V
CC  
V
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
DESCRIPTION  
This 16-bit bus transceiver and register is designed  
for 1.65-V to 3.6-V VCC operation.  
The SN74ALVCH16646 can be used as two 8-bit  
transceivers or one 16-bit transceiver. Data on the A  
or B bus is clocked into the registers on the  
low-to-high transition of the appropriate clock (CLKAB  
or CLKBA) input. Figure  
fundamental bus-management functions that can be  
performed with the SN74ALVCH16646.  
V
CC  
V
CC  
1
illustrates the four  
2A7  
2A8  
2B7  
2B8  
GND  
GND  
2SBA  
2CLKBA  
2OE  
2SAB  
2CLKAB  
2DIR  
Output-enable (OE) and direction-control (DIR) inputs  
are provided to control the transceiver functions. In  
the transceiver mode, data present at the  
high-impedance port may be stored in either register  
or in both. The select-control (SAB and SBA) inputs  
can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the  
typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR  
determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in  
one register and/or B data may be stored in the other register.  
When an output function is disabled, the input function is still enabled and may be used to store and transmit  
data. Only one of the two buses, A or B, can be driven at a time.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16646 is characterized for operation from -40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...18

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74ALVCH16646DGVRE4 替代型号

型号 品牌 替代类型 描述 数据表
74ALVCH16646DGVRG4 TI

完全替代

 ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC,
SN74ALVCH16646DGVR TI

类似代替

 具有三态输出的 16 位总线收发器和寄存器 | DGV | 56 | -40 to 85

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