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74ALVCH16652DGG PDF预览

74ALVCH16652DGG

更新时间: 2024-11-20 11:15:15
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
18页 255K
描述
16-bit transceiver/register with dual enable; 3-stateProduction

74ALVCH16652DGG 数据手册

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74ALVCH16652  
16-bit transceiver/register with dual enable; 3-state  
Rev. 3 — 12 September 2018  
Product data sheet  
1. General description  
The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-  
type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the  
data bus or from the internal storage registers.  
Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock  
inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and nSBA) or output enable  
(nOEAB and nOEBA) control inputs.  
Depending on the select inputs nSAB and nSBA data can directly go from input to output (real-time  
mode) or data can be controlled by the clock (storage mode), when OE inputs permit this operating  
mode.  
The output enable inputs nOEAB and nOEBA determine the operation mode of the transceiver.  
When nOEAB is LOW, no data transmission from nBn to nAn is possible and when nOEBA is  
HIGH, no data transmission from nBn to nAn is possible.  
When nSAB and nSBA are in the real-time transfer mode, it is also possible to store data without  
using the internal D-type flip-flops by simultaneously enabling nOEAB and nOEBA. In this  
configuration each output reinforces its input.  
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
2. Features and benefits  
Wide supply voltage range of 1.2 V to 3.6 V  
CMOS low power consumption  
Direct interface with TTL levels  
Current drive ±24 mA at VCC = 3.0 V.  
MULTIBYTE flow-through standard pin-out architecture  
Low inductance multiple VCC and GND pins for minimum noise and ground bounce  
All data inputs have bushold  
Output drive capability 50 Ω transmission lines at 85 °C  
Complies with JEDEC standards:  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V  
CDM JESD22-C101E exceeds 1000 V  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74ALVCH16652DGG −40 °C to +85 °C  
TSSOP56  
plastic thin shrink small outline package; 56 leads; SOT364-1  
body width 6.1 mm  
 
 
 

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