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74ALVCH16646DGG PDF预览

74ALVCH16646DGG

更新时间： 2024-09-17 11:14:35
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
17页 245K
描述
16-bit bus transceiver/register; 3-stateProduction

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74ALVCH16646DGG 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TSOP2,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.36
Is Samacsys：N其他特性：IT ALSO OPERATES AT 3 TO 3.6
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER湿度敏感等级：2
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：260传播延迟（tpd）：5.6 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
Base Number Matches：1

74ALVCH16646DGG 数据手册

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74ALVCH16646  
16-bit bus transceiver/register; 3-state  
Rev. 3 — 11 September 2018  
Product data sheet  
1. General description  
The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-state outputs,  
D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from  
the internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal registers, as the  
appropriate clock (nCPAB or nCPBA) goes to a HIGH logic level. Output enable (nOE) and  
direction (nDIR) inputs are provided to control the transceiver function. In the transceiver mode,  
data present at the high-impedance port may be stored in either the ‘A’ or ‘B’ register, or in both.  
The select source inputs (nSAB and nSBA) can multiplex stored and real-time (transparent mode)  
data. The direction (nDIR) input determines which bus will receive data when nOE is active (LOW).  
In the isolation mode (nOE = HIGH), ‘A’ data may be stored in the ‘B’ register and/or ‘B’ data may  
be stored in the ‘A’ register.  
When an output function is disabled, the input function is still enabled and may be used to store  
and transmit data. Only one of the two buses, ‘A’ or ‘B’ may be driven at a time.  
To ensure the high impedance state during power up or power down, nOE should be tied to VCC  
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/  
current-sourcing capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
2. Features and benefits  
•
Wide supply voltage range of 2.3 V to 3.6 V  
•
•
•
•
•
•
•
•
CMOS low power consumption  
Direct interface with TTL levels  
Current drive ±24 mA at VCC = 3.0 V.  
MULTIBYTE flow-through standard pin-out architecture  
Low inductance multiple VCC and GND pins for minimize noise and ground bounce  
All data inputs have bushold  
Output drive capability 50 Ω transmission lines at 85 °C  
Complies with JEDEC standards:  
•
•
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
•
ESD protection:  
•
•
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V  
CDM JESD22-C101E exceeds 1000 V  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74ALVCH16646DGG −40 °C to +85 °C  
TSSOP56  
plastic thin shrink small outline package; 56 leads; SOT364-1  
body width 6.1 mm  
 
 
 
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