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74ALVCH162601DGG PDF预览

74ALVCH162601DGG

更新时间： 2024-11-10 11:14:15
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
15页 228K
描述
18-bit universal bus transceiver with 30 Ohm termination resistor; 3-stateProduction

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74ALVCH162601DGG 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TSSOP,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.24
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER湿度敏感等级：2
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：6.4 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.2 V
标称供电电压 (Vsup)：2.4 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
Base Number Matches：1

74ALVCH162601DGG 数据手册

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74ALVCH162601  
18-bit universal bus transceiver with 30 Ω termination  
resistor; 3-state  
Rev. 2 — 13 August 2018  
Product data sheet  
1. General description  
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting 3-state bus  
compatible outputs in both send and receive directions. Data flow in each direction is controlled by  
output enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CPAB and CPBA)  
inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.  
When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is  
LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When  
OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance  
state. The clocks can be controlled with the clock-enable inputs (CEBA and CEAB).  
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.  
To ensure the high impedance state during power up or power down, OEBA and OEAB should  
be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the  
current-sinking/current-sourcing capability of the driver.  
The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or LOW output stage.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
2. Features and benefits  
•
CMOS low power consumption  
•
•
•
•
•
•
MultiByte flow-through standard pin-out architecture  
Low inductance multiple VCC and GND pins for minimum noise and ground bounce  
Direct interface with TTL levels  
Bus hold on data inputs  
Integrated 30 Ω termination resistors.  
Complies with JEDEC standards:  
•
•
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
•
ESD protection:  
•
•
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V  
CDM JESD22-C101E exceeds 1000 V  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range  
Name  
Description  
Version  
74ALVCH162601DGG −40 °C to +85 °C  
TSSOP56  
plastic thin shrink small outline package;  
56 leads; body width 6.1 mm  
SOT364-1  
 
 
 
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