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74ALVCH162721PA PDF预览

74ALVCH162721PA

更新时间: 2024-11-18 14:47:03
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
6页 66K
描述
TSSOP-56, Tube

74ALVCH162721PA 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP56,.3,20针数:56
Reach Compliance Code:not_compliant风险等级:5.91
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:150000000 Hz最大I(ol):0.012 A
湿度敏感等级:1功能数量:20
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:3.3 V
Prop。Delay @ Nom-Sup:4.3 ns认证状态:Not Qualified
子类别:FF/Latches标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
Base Number Matches:1

74ALVCH162721PA 数据手册

 浏览型号74ALVCH162721PA的Datasheet PDF文件第2页浏览型号74ALVCH162721PA的Datasheet PDF文件第3页浏览型号74ALVCH162721PA的Datasheet PDF文件第4页浏览型号74ALVCH162721PA的Datasheet PDF文件第5页浏览型号74ALVCH162721PA的Datasheet PDF文件第6页 
IDT74ALVCH162721  
3.3V CMOS 20-BIT  
FLIP-FLOP WITH 3-STATE  
OUTPUTS AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
This20-bitflip-flopisbuiltusingadvanceddualmetalCMOStechnology.The  
20 flip-flops of the ALVCH162721 are edge-triggered D-type flip-flops with  
qualifiedclockstorage.Onthepositivetransitionoftheclock(CLK)input,the  
deviceprovidestruedataattheQoutputsiftheclock-enable(CLKEN)inputis  
low. If CLKEN is high, no data is stored.  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Available in TSSOP package  
Abufferedoutput-enable(OE)inputplacesthe20outputsineitheranormal  
logicstate(highorlow)orahigh-impedancestate.Inthehigh-impedancestate,  
theoutputsneitherloadnordrivethebuslinessignificantly.Thehigh-impedance  
stateandincreaseddriveprovidethecapabilitytodrivebuslineswithoutneed  
forinterfaceorpullupcomponents.OEdoesnotaffecttheinternaloperationof  
the flip-flops. Old data can be retained or new data can be entered while the  
outputsareinthehigh-impedancestate.  
TheALVCH162721hasseriesresistorsinthedeviceoutputstructurewhich  
will significantly reduce line noise when used with light loads. This driver has  
beendesignedtodrive±12mAatthedesignatedthresholdlevels.  
The ALVCH162721 has “bus-hold” which retains the inputs’ last state  
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputsand  
eliminatestheneedforpull-up/downresistor.  
DRIVE FEATURES:  
• Balanced Output Drivers: ±12mA  
• Low switching noise  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
FUNCTIONALBLOCKDIAGRAM  
1
OE  
56  
CLK  
29  
CLKEN  
CE  
C1  
1D  
2
Q1  
55  
D1  
To 19 Other Channels  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2004  
1
© 2004 Integrated Device Technology, Inc.  
DSC-4566/2  

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