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74ALVCH16373DGG,118 PDF预览

74ALVCH16373DGG,118

更新时间： 2024-09-16 19:47:27
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
18页 473K
描述
IC ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48, Bus Driver/Transceiver

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74ALVCH16373DGG,118 技术参数

生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：48
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.6系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G48长度：12.5 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：5.9 ns
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.2 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

74ALVCH16373DGG,118 数据手册

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74ALVCH16373  
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state  
Rev. 04 — 31 May 2010  
Product data sheet  
1. General description  
The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for  
each latch and 3-state outputs for bus oriented applications.  
Incorporates bus hold data inputs which eliminate the need for external pull-up or  
pull-down resistors to hold unused inputs.  
One latch enable (LE) input and one output enable (OE) are provided per 8-bit section.  
The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state  
true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition  
the latches are transparent, therefore a latch output will change each time its  
corresponding D-input changes.  
When LE is LOW, the latches store the information that was present at the nDn inputs at a  
set-up time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents  
of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the  
high-impedance OFF-state. Operation of the OE input does not affect the state of the  
latches.  
2. Features and benefits  
„ Wide supply voltage range from 1.2 V to 3.6 V  
„ Complies with JEDEC standard JESD8-B  
„ CMOS low power consumption  
„ MULTIBYTE flow-through standard pin-out architecture  
„ Low inductance multiple VCC and GND pins for minimum noise and ground bounce  
„ Direct interface with TTL levels  
„ All data inputs have bus hold  
„ Output drive capability 50 Ω transmission lines at 85 °C  
„ Current drive ±24 mA at VCC = 3.0 V  
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