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74ALVCH16373DGGRG4 PDF预览

74ALVCH16373DGGRG4

更新时间： 2024-11-21 05:05:51
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
19页 489K
描述
16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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74ALVCH16373DGGRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP48,.3,20针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.14
控制类型：ENABLE LOW/HIGH计数方向：UNIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：3.6 ns
传播延迟（tpd）：4.9 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceiver
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：6.1 mmBase Number Matches：1

74ALVCH16373DGGRG4 数据手册

 浏览型号74ALVCH16373DGGRG4的Datasheet PDF文件第2页浏览型号74ALVCH16373DGGRG4的Datasheet PDF文件第3页浏览型号74ALVCH16373DGGRG4的Datasheet PDF文件第4页浏览型号74ALVCH16373DGGRG4的Datasheet PDF文件第5页浏览型号74ALVCH16373DGGRG4的Datasheet PDF文件第6页浏览型号74ALVCH16373DGGRG4的Datasheet PDF文件第7页 
SN74ALVCH16373  
16-BIT TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES020I–JULY 1995–REVISED NOVEMBER 2005  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 3.6 ns at 3.3 V  
2
3
±24-mA Output Drive at 3.3 V  
4
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
5
6
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
7
V
CC  
V
CC  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
9
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
XXXX  
DESCRIPTION/ORDERING INFORMATION  
This 16-bit transparent D-type latch is designed for  
1.65-V to 3.6-V VCC operation.  
V
CC  
V
CC  
The SN74ALVCH16373 is particularly suitable for  
implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers. This device can  
be used as two 8-bit latches or one 16-bit latch.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is taken  
low, the Q outputs are latched at the levels set up at  
the D inputs.  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
A buffered output-enable (OE) input can be used to  
place the eight outputs in either a normal logic state  
(high or low logic levels) or the high-impedance state.  
In the high-impedance state, the outputs neither  
load nor drive the buslines significantly. The  
high-impedance state and the increased drive provide  
the capability to drive bus lines without need for  
interface or pullup components. OE does not affect  
internal operations of the latch. Old data can be  
retained or new data can be entered while the  
outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...19

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74ALVCH16373DGGRG4 替代型号

型号 品牌 替代类型 描述 数据表
74ALVCH16373DGGE4 TI

完全替代

 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74ALVCH16373GRE4 TI

完全替代

 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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74ALVCH16373DLRG4 TI

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74ALVCH16373DT STMICROELECTRONICS

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74ALVCH16373DTR STMICROELECTRONICS

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74ALVCH16373GRDR TI

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 		16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74ALVCH16373GRE4 TI

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 		16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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