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74ALVCH16374 PDF预览

74ALVCH16374

更新时间: 2024-11-17 22:56:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 100K
描述
Low Voltage 16-Bit D-Type Flip-Flop with Bushold

74ALVCH16374 数据手册

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September 2001  
Revised February 2002  
74ALVCH16374  
Low Voltage 16-Bit D-Type Flip-Flop with Bushold  
General Description  
Features  
The ALVCH16374 contains sixteen non-inverting D-type  
flip-flops with 3-STATE outputs and is intended for bus ori-  
ented applications. The device is byte controlled. A buff-  
ered clock (CP) and output enable (OE) are common to  
each byte and can be shorted together for full 16-bit opera-  
tion.  
1.65V to 3.6V VCC supply operation  
3.6V tolerant control inputs and outputs  
Bushold on data inputs eliminates the need for external  
pull-up/pull-down resistors  
tPD  
The ALVCH16374 data inputs include active bushold cir-  
cuitry, eliminating the need for external pull-up resistors to  
hold unused or floating data inputs at a valid logic level.  
4.2 ns max for 3.0V to 3.6V VCC  
5.3 ns max for 2.3V to 2.7V VCC  
7.8 ns max for 1.65V to 1.95V VCC  
The 74ALVCH16374 is designed for low voltage (1.65V to  
3.6V) VCC applications with output compatibility up to 3.6V.  
Uses patented noise/EMI reduction circuitry  
Latch-up conforms to JEDEC JED78  
ESD performance:  
The 74ALVCH16374 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Ordering Code:  
Package  
Order Number  
Package Descriptions  
Number  
74ALVCH16374T  
(Note 1)  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 1: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
© 2002 Fairchild Semiconductor Corporation  
DS500627  
www.fairchildsemi.com  

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