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74ALVCH162721PF PDF预览

74ALVCH162721PF

更新时间： 2024-09-16 21:09:59
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路触发器电视
页数 文件大小 规格书
6页 87K
描述
TVSOP-56, Tube

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中文翻译

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74ALVCH162721PF 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TVSOP
针数：56Reach Compliance Code：not_compliant
风险等级：5.91JESD-30 代码：R-PDSO-G56
JESD-609代码：e0负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：150000000 Hz
最大I（ol）：0.012 A湿度敏感等级：1
功能数量：20端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.25,16
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：3.3 VProp。Delay @ Nom-Sup：4.3 ns
认证状态：Not Qualified子类别：FF/Latches
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
触发器类型：POSITIVE EDGEBase Number Matches：1

74ALVCH162721PF 数据手册

 浏览型号74ALVCH162721PF的Datasheet PDF文件第2页浏览型号74ALVCH162721PF的Datasheet PDF文件第3页浏览型号74ALVCH162721PF的Datasheet PDF文件第4页浏览型号74ALVCH162721PF的Datasheet PDF文件第5页浏览型号74ALVCH162721PF的Datasheet PDF文件第6页 
3.3V CMOS 20-BIT  
IDT74ALVCH162721  
FLIP-FLOP WITH 3-STATE  
OUTPUTS AND BUS-HOLD  
DESCRIPTION:  
FEATURES:  
This 20-bit flip-flop is built using advanced dual metal CMOS technol-  
–
–
–
0.5 MICRON CMOS Technology  
TypicaltSK(0) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
ogy. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type  
flip-flops with qualified clock storage. On the positive transition of the  
clock (CLK) input, the device provides true data at the Q outputs if the  
clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored.  
–
A buffered output-enable (OE) input places the 20 outputs in either a  
normal logic state (high or low) or a high-impedance state. In the high-  
impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the  
capability to drive bus lines without need for interface or pullup compo-  
nents. OE does not affect the internal operation of the flip-flops. Old data  
can be retained or new data can be entered while the outputs are in the  
high-impedance state.  
–
–
–
–
–
–
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
Drive Features for ALVCH162721:  
–
–
Balanced Output Drivers: ±12mA  
Low switching noise  
The ALVCH162721 has series resistors in the device output structure  
which will significantly reduce line noise when used with light loads. This  
driver has been designed to drive ±12mA at the designated threshold  
levels.  
APPLICATIONS:  
• 3.3V High Speed Systems  
• 3.3V and lower voltage computing systems  
The ALVCH162721 has “bus-hold” which retains the inputs’ last state  
whenever the input goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistor.  
Functional Block Diagram  
1
OE  
56  
CLK  
29  
CLKEN  
CE  
C1  
1D  
2
Q1  
55  
D1  
To 19 Other Channels  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
MARCH1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4566/-  
123456

中文翻译

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