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74ALVCH162721GRE4 PDF预览

74ALVCH162721GRE4

更新时间： 2024-11-06 14:47:03
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路触发器
页数 文件大小 规格书
14页 338K
描述
3.3-V 20-Bit Flip-Flop With 3-State Outputs 56-TSSOP -40 to 85

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74ALVCH162721GRE4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP56,.3,20
针数：56Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.2
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：150000000 Hz最大I（ol）：0.012 A
湿度敏感等级：1位数：20
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：5.3 ns
传播延迟（tpd）：6.7 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：6.1 mmBase Number Matches：1

74ALVCH162721GRE4 数据手册

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SN74ALVCH162721  
3.3-V 20-BIT FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES055G–DECEMBER 1995–REVISED SEPTEMBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
•
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OE  
Q1  
CLK  
D1  
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
2
3
Q2  
D2  
Output Ports Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
4
GND  
Q3  
GND  
D3  
5
6
Q4  
D4  
•
ESD Protection Exceeds 2000 V Per  
7
V
CC  
V
CC  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
8
Q5  
Q6  
D5  
D6  
9
•
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Q7  
GND  
Q8  
D7  
GND  
D8  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Q9  
D9  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
Q10  
Q11  
Q12  
Q13  
GND  
Q14  
Q15  
Q16  
D10  
D11  
D12  
D13  
GND  
D14  
D15  
D16  
NOTE: For tape-and-reel order entry, the DGGR package is  
abbreviated to GR.  
DESCRIPTION  
This 20-bit flip-flop is designed for low-voltage 1.65-V  
to 3.6-V VCC operation.  
V
CC  
V
CC  
Q17  
Q18  
GND  
Q19  
Q20  
NC  
D17  
D18  
The 20 flip-flops of the SN74ALVCH162721 are  
edge-triggered D-type flip-flops with qualified clock  
storage. On the positive transition of the clock (CLK)  
input, the device provides true data at the Q outputs if  
the clock-enable (CLKEN) input is low. If CLKEN is  
high, no data is stored.  
GND  
D19  
D20  
CLKEN  
A buffered output-enable (OE) input places the 20  
outputs in either a normal logic state (high or low  
level) or the high-impedance state. In the  
high-impedance state, the outputs neither load nor  
drive the bus lines significantly. The high-impedance  
NC − No internal connection  
state and increased drive provide the capability to drive bus lines without interface or pullup components. OE  
does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and  
undershoot.  
The SN74ALVCH162721 is characterized for operation from -40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

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74ALVCH162721GRE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH162721GR TI

完全替代

 3.3-V 20-Bit Flip-Flop With 3-State Outputs 56-TSSOP -40 to 85
SN74ALVCH16721DGG TI

完全替代

 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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74ALVCH162721PV IDT

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74ALVCH162820PF8 IDT

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74ALVCH162820PV IDT

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74ALVCH162827 NXP

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74ALVCH162827DG NXP

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