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74ALVCH162601DLG4

更新时间： 2024-11-06 01:20:43
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德州仪器 - TI 输出元件
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15页 361K
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18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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74ALVCH162601DLG4 数据手册

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SN74ALVCH162601  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES026H–JULY 1995–REVISED AUGUST 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
•
•
Member of the Texas Instruments Widebus™  
Family  
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEAB  
LEAB  
A1  
1
56 CLKENAB  
55 CLKAB  
2
3
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
B1  
UBT™ (Universal Bus Transceiver) Combines  
D-Type Latches and D-Type Flip-Flops for  
Operation in Transparent, Latched, Clocked,  
or Clock-Enabled Modes  
4
GND  
A2  
GND  
B2  
5
6
A3  
B3  
7
V
CC  
V
CC  
•
•
B-Port Outputs Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
8
A4  
A5  
B4  
B5  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
A6  
GND  
A7  
B6  
GND  
B7  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
A8  
B8  
•
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
A9  
B9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
NOTE: For tape-and-reel order entry, the DGGR package is  
abbreviated to GR.  
V
CC  
V
CC  
A16  
A17  
B16  
B17  
DESCRIPTION  
GND  
A18  
OEBA  
LEBA  
GND  
B18  
CLKBA  
CLKENBA  
This 18-bit universal bus transceiver is designed for  
1.65-V to 3.6-V VCC operation.  
The SN74ALVCH162601 combines D-type latches  
and D-type flip-flops to allow data flow in transparent,  
latched, clocked, and clock-enabled modes.  
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),  
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and  
CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When  
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is  
stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active.  
When OEAB is high, the outputs are in the high-impedance state.  
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.  
The B-port outputs include equivalent 26-Ω series resistors to reduce overshoot and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH162601 is characterized for operation from -40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC, UBT are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

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74ALVCH162601DLG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH162601DLR TI

类似代替

 18-Bit Universal Bus Transceiver With 3-State Outputs 56-SSOP -40 to 85

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