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74AHC573D/T3 PDF预览

74AHC573D/T3

更新时间: 2024-09-13 14:50:15
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
17页 98K
描述
IC AHC/VHC/H/U/V SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20, Bus Driver/Transceiver

74AHC573D/T3 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.07Is Samacsys:N
系列:AHC/VHC/H/U/VJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260传播延迟(tpd):19.5 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

74AHC573D/T3 数据手册

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74AHC573; 74AHCT573  
Octal D-type transparant latch; 3-state  
Rev. 03 — 24 April 2008  
Product data sheet  
1. General description  
The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7A.  
The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuring  
separate D-type inputs for each latch and 3-state true outputs for bus oriented  
applications. A latch enable input (LE) and an output enable input (OE) are common to all  
latches.  
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the  
latches are transparent, i.e. a latch output will change state each time its corresponding  
Dn input changes. When pin LE is LOW, the latches store the information that is present  
at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.  
When pin OE is LOW, the contents of the 8 latches are available at the outputs. When  
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE  
input does not affect the state of the latches.  
The 74AHC573; 74AHCT573 is functionally identical to:  
74AHC563; 74AHCT563 which has inverted outputs and a different pin arrangement  
74AHC373; 74AHCT373 which has a different pin arrangement  
2. Features  
I Balanced propagation delays  
I All inputs have a Schmitt-trigger action  
I Common 3-state output enable input  
I Functionally identical to the 74AHC563; 74AHCT563 and 74AHC373; 74AHCT373  
I Inputs accept voltages higher than VCC  
I Input levels:  
N For 74AHC573: CMOS input level  
N For 74AHCT573: TTL input level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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