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74AHC594BQ PDF预览

74AHC594BQ

更新时间: 2024-11-06 11:11:31
品牌 Logo 应用领域
安世 - NEXPERIA 逻辑集成电路触发器
页数 文件大小 规格书
20页 301K
描述
8-bit shift register with output registerProduction

74AHC594BQ 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:2.50 X 3.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-763-1, DHVQFN-16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.26
计数方向:RIGHT系列:HC/UH
JESD-30 代码:R-PQCC-N16JESD-609代码:e4
长度:3.5 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):15.1 ns认证状态:Not Qualified
座面最大高度:1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:2.5 mm
最小 fmax:90 MHzBase Number Matches:1

74AHC594BQ 数据手册

 浏览型号74AHC594BQ的Datasheet PDF文件第2页浏览型号74AHC594BQ的Datasheet PDF文件第3页浏览型号74AHC594BQ的Datasheet PDF文件第4页浏览型号74AHC594BQ的Datasheet PDF文件第5页浏览型号74AHC594BQ的Datasheet PDF文件第6页浏览型号74AHC594BQ的Datasheet PDF文件第7页 
74AHC594; 74AHCT594  
8-bit shift register with output register  
Rev. 4 — 7 July 2021  
Product data sheet  
1. General description  
The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible with  
Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.  
The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register that  
feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding  
clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is  
provided for cascading purposes.  
Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect  
both clocks together, the shift register will always be one count pulse ahead of the storage register.  
2. Features and benefits  
Wide supply voltage range from 2.0 V to 5.5 V  
Balanced propagation delays  
All inputs have Schmitt-trigger action  
Overvoltage tolerant inputs to 5.5 V  
High noise immunity  
CMOS low power dissipation  
8-bit serial-in, parallel-out shift register with storage  
Independent direct overriding clears on shift and storage registers  
Independent clocks for shift and storage registers  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A  
Input levels:  
For 74AHC594: CMOS level  
For 74AHCT594: TTL level  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Multiple package options  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Applications  
Serial-to parallel data conversion  
Remote control holding register  
 
 
 

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