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74AHC594PW-T PDF预览

74AHC594PW-T

更新时间: 2024-12-01 12:58:27
品牌 Logo 应用领域
恩智浦 - NXP 移位寄存器
页数 文件大小 规格书
29页 154K
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74AHC594PW-T 数据手册

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74AHC594; 74AHCT594  
8-bit shift register with output register  
Rev. 01 — 4 July 2006  
Product data sheet  
1. General description  
The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7A.  
The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register  
that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct  
overriding clears (SHR and STR) are provided on both the shift and storage registers.  
A serial output (Q7S) is provided for cascading purposes.  
Both the shift and storage register clocks are positive-edge triggered. If the user wishes to  
connect both clocks together, the shift register will always be one count pulse ahead of the  
storage register.  
2. Features  
Wide supply voltage range from 2.0 V to 5.5 V  
8-bit serial-in, parallel-out shift register with storage  
Independent direct overriding clears on shift and storage registers  
Independent clocks for shift and storage registers  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Input levels:  
CMOS levels: 74AHC594 only  
TTL levels: 74AHCT594 only  
ESD protection:  
HBM JESD22-A114-C exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101-C exceeds 1000 V  
Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Applications  
Serial-to parallel data conversion  
Remote control holding register  

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