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74AHC594D-Q100 PDF预览

74AHC594D-Q100

更新时间: 2024-11-02 02:56:59
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
24页 764K
描述
8-bit shift register with output register

74AHC594D-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.57
计数方向:RIGHT系列:AHC/VHC/H/U/V
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):15.1 ns筛选级别:AEC-Q100
座面最大高度:1.75 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:70 MHzBase Number Matches:1

74AHC594D-Q100 数据手册

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74AHC594-Q100;  
74AHCT594-Q100  
8-bit shift register with output register  
Rev. 2 — 4 July 2013  
Product data sheet  
1. General description  
The 74AHC594-Q100; 74AHCT594-Q100 is a high-speed Si-gate CMOS device and is  
pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with  
JEDEC standard No. 7A.  
The 74AHC594-Q100; 74AHCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out  
shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and  
STCP) and direct overriding clears (SHR and STR) are provided on both the shift and  
storage registers. A serial output (Q7S) is provided for cascading purposes.  
Both the shift and storage register clocks are positive-edge triggered. If the user wishes to  
connect both clocks together, the shift register is always one count pulse ahead of the  
storage register.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Balanced propagation delays  
All inputs have Schmitt trigger actions  
Inputs accept voltages higher than VCC  
Wide supply voltage range from 2.0 V to 5.5 V  
8-bit serial-in, parallel-out shift register with storage  
Independent direct overriding clears on shift and storage registers  
Independent clocks for shift and storage registers  
Latch-up performance exceeds 100 mA per JESD78 Class II  
Input levels:  
For 74AHC594-Q100: CMOS level  
For 74AHCT594-Q100: TTL level  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )  
Multiple package options  

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