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74AC11374DWR PDF预览

74AC11374DWR

更新时间: 2024-11-20 02:58:35
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
7页 118K
描述
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS

74AC11374DWR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP24,.4针数:24
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.48
系列:ACJESD-30 代码:R-PDSO-G24
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 V传播延迟(tpd):10.2 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

74AC11374DWR 数据手册

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74AC11374  
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCAS214A – JULY 1987 – REVISED APRIL 1996  
DB, DW, OR NT PACKAGE  
(TOP VIEW)  
Eight D-Type Flip-Flops in a Single Package  
3-State Bus-Driving True Outputs  
Full Parallel Access for Loading  
1Q  
2Q  
OE  
1D  
2D  
3D  
4D  
V
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
Flow-Through Architecture Optimizes  
PCB Layout  
3Q  
3
4Q  
4
Center-Pin V  
Minimize High-Speed Switching Noise  
and GND Configurations  
CC  
GND  
GND  
GND  
GND  
5Q  
5
6
CC  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
7
V
CC  
5D  
8
500-mA Typical Latch-Up Immunity at  
125°C  
9
6D  
10  
11  
12  
6Q  
7D  
Package Options Include Plastic  
Small-Outline (DW) and Shrink  
Small-Outline (DB) Packages, and Standard  
Plastic 300-mil DIPs (NT)  
7Q  
8D  
8Q  
CLK  
description  
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively  
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
The eight flip-flops of the 74AC11374 are edge-triggered D-type flip-flops. On the positive transition of the clock,  
the Q outputs are set to the logic levels set up at the D inputs.  
The output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low  
logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus  
lines signigicantly. The high-impedance third state provides the capability to drive the bus lines in a  
bus-organized system without need for interface or pullup components.  
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The 74AC11374 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
H
L
L
L
L
H
X
X
X
X
Q
Q
Q
0
0
0
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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