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74AC11379_10 PDF预览

74AC11379_10

更新时间: 2024-11-12 02:58:19
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
7页 100K
描述
QUAD D- TYPE FLIP FLOP WITH DATA ENABLE

74AC11379_10 数据手册

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ꢇ ꢈꢂꢉꢊ ꢉꢋꢌ ꢍꢎꢏ ꢊꢐ ꢑꢒ ꢎ ꢋꢐ ꢑꢓ  
SCAS104 − MARCH 1990 − REVISED APRIL 1993  
DW OR N PACKAGE  
(TOP VIEW)  
Contains Four Flip-Flops with Double-Rail  
Outputs  
Clock Enable Latched to Avoid False  
1Q  
2Q  
1Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Clocking  
CLKEN  
1D  
Applications Include: Buffer/Storage  
Registers, Shift Registers, Pattern  
Generators  
2Q  
GND  
GND  
GND  
GND  
3Q  
2D  
V
V
CC  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
3D  
Center-Pin V  
and GND Pin  
Configurations Minimize High-Speed  
Switching Noise  
4D  
CC  
3Q  
CLK  
4Q  
4Q  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
500-mA Typical Latch-Up Immunity at  
125°C  
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
description  
These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input.  
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the  
positive-going edge of the clock pulse if the clock-enable input (CLKEN) is low. Clock triggering occurs at a  
particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock  
input is at either the high or low level, the data (D) input signal has no effect at the output. The circuits are  
designed to prevent false clocking by transitions at the clock-enable (CLKEN) input.  
The 74AC11379 is characterized for operation from − 40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUTS  
CLKEN  
CLK  
X
D
X
H
L
Q
Q
H
L
Q
Q
0
0
H
L
L
L
H
X
L
X
Q
Q
0
0
EPIC is a trademark of Texas Instruments Incorporated.  
ꢌꢥ  
Copyright 1993, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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