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74AC11478

更新时间： 2024-11-11 12:50:31
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
7页 114K
描述
OCTAL DUAL-RANK D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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74AC11478 数据手册

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SCAS182 − APRIL 1989 − REVISED APRIL 1993  
DW OR NT PACKAGE  
(TOP VIEW)  
• Specifically Designed for Data  
Synchronization Applications  
• 3-State Outputs Drive Bus Lines Directly  
1Q  
2Q  
3Q  
4Q  
GND  
GND  
GND  
GND  
5Q  
OE  
1
24  
• Flow-Through Architecture Optimizes PCB  
2
23 1D  
22 2D  
Layout  
3
4
21  
20  
19  
18  
17  
16  
15  
14  
13  
3D  
4D  
V
• Center-Pin V  
and GND Pin  
Configurations Minimize High-Speed  
Switching Noise  
CC  
5
6
CC  
7
V
CC  
•
EPIC (Enhanced-Performance Implanted  
CMOS ) 1-µm Process  
8
5D  
6D  
7D  
8D  
9
• Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
10  
11  
12  
6Q  
7Q  
8Q  
CLK  
description  
The 74AC11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization  
applications in which the normal setup and hold time specifications are frequently violated.  
Synchronization of two digital signals operating at different frequencies is a common system problem. This  
problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution,  
however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the  
setup or hold time of a flip-flop is violated, the output response is uncertain. A flip-flop is metastable if its output  
hangs up in the region between V and V . The metastable condition lasts until the flip-flop recovers into one  
IL  
IH  
of its two stable states. With conventional flip-flops, this recovery time can be longer than the specified maximum  
propagation delay.  
The problem of metastability is typically solved by adding an additional layer of synchronization. This dual-rank  
approach is employed in the 74AC11478. The probability of the second stage entering the metastable state is  
exponentially reduced by this dual-rank architecture. The 74AC11478 provides a one-chip solution for system  
designers in asynchronous applications.  
The 74AC11478 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
†
CLK  
OE  
D
H
L
L
L
X
↑
↑
L
X
L
H
X
Z
L
H
Q
0
†
Data presented at the  
D inputs  
requires two clock cycles to appear at  
the Q outputs.  
EPIC is a trademark of Texas Instruments Incorporated.  
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Copyright 1993, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567

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与74AC11478相关器件

型号 品牌 获取价格 描述 数据表
74AC11478DW TI

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 		Octal Dual-Rank D-Type Flip-Flops With 3-State Outputs 24-SOIC -40 to 85
74AC11478DWR TI

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 		AC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOIC-24
74AC11478NT ROCHESTER

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 		Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-
74AC11478NT TI

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 		Octal Dual-Rank D-Type Flip-Flops With 3-State Outputs 24-PDIP -40 to 85
74AC11520 TI

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 		8-BIT IDENTITY COMPARATOR
74AC11520_09 TI

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 		8-BIT IDENTITY COMPARATOR
74AC11520D YAGEO

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 		Identity Comparator, AC Series, 8-Bit, Inverted Output, CMOS, PDSO20
74AC11520D-T YAGEO

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 		Identity Comparator, AC Series, 8-Bit, Inverted Output, CMOS, PDSO20
74AC11520DW ETC

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 		Identity Comparator
74AC11520DWR TI

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 		AC SERIES, 8-BIT IDENTITY COMPARATOR, INVERTED OUTPUT, PDSO20, PLASTIC, SOIC-20

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