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74AC11379DWR PDF预览

74AC11379DWR

更新时间: 2024-11-11 14:35:35
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
7页 100K
描述
AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO20, PLASTIC, SOIC-20

74AC11379DWR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, SOIC-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
其他特性:WITH HOLD MODE系列:AC
JESD-30 代码:R-PDSO-G20长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
位数:4功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):14 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:100 MHzBase Number Matches:1

74AC11379DWR 数据手册

 浏览型号74AC11379DWR的Datasheet PDF文件第2页浏览型号74AC11379DWR的Datasheet PDF文件第3页浏览型号74AC11379DWR的Datasheet PDF文件第4页浏览型号74AC11379DWR的Datasheet PDF文件第5页浏览型号74AC11379DWR的Datasheet PDF文件第6页浏览型号74AC11379DWR的Datasheet PDF文件第7页 
ꢇ ꢈꢂꢉꢊ ꢉꢋꢌ ꢍꢎꢏ ꢊꢐ ꢑꢒ ꢎ ꢋꢐ ꢑꢓ  
SCAS104 − MARCH 1990 − REVISED APRIL 1993  
DW OR N PACKAGE  
(TOP VIEW)  
Contains Four Flip-Flops with Double-Rail  
Outputs  
Clock Enable Latched to Avoid False  
1Q  
2Q  
1Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Clocking  
CLKEN  
1D  
Applications Include: Buffer/Storage  
Registers, Shift Registers, Pattern  
Generators  
2Q  
GND  
GND  
GND  
GND  
3Q  
2D  
V
V
CC  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
3D  
Center-Pin V  
and GND Pin  
Configurations Minimize High-Speed  
Switching Noise  
4D  
CC  
3Q  
CLK  
4Q  
4Q  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
500-mA Typical Latch-Up Immunity at  
125°C  
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
description  
These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input.  
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the  
positive-going edge of the clock pulse if the clock-enable input (CLKEN) is low. Clock triggering occurs at a  
particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock  
input is at either the high or low level, the data (D) input signal has no effect at the output. The circuits are  
designed to prevent false clocking by transitions at the clock-enable (CLKEN) input.  
The 74AC11379 is characterized for operation from − 40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUTS  
CLKEN  
CLK  
X
D
X
H
L
Q
Q
H
L
Q
Q
0
0
H
L
L
L
H
X
L
X
Q
Q
0
0
EPIC is a trademark of Texas Instruments Incorporated.  
ꢌꢥ  
Copyright 1993, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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