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74AC11478DW

更新时间： 2024-11-11 20:03:03
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 104K
描述
Octal Dual-Rank D-Type Flip-Flops With 3-State Outputs 24-SOIC -40 to 85

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74AC11478DW 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP24,.4针数：24
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.91系列：AC
JESD-30 代码：R-PDSO-G24长度：15.4 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：55000000 Hz最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3/5 V传播延迟（tpd）：18.4 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.5 mmBase Number Matches：1

74AC11478DW 数据手册

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SCAS182 − APRIL 1989 − REVISED APRIL 1993  
DW OR NT PACKAGE  
(TOP VIEW)  
• Specifically Designed for Data  
Synchronization Applications  
• 3-State Outputs Drive Bus Lines Directly  
1Q  
2Q  
3Q  
4Q  
GND  
GND  
GND  
GND  
5Q  
OE  
1
24  
• Flow-Through Architecture Optimizes PCB  
2
23 1D  
22 2D  
Layout  
3
4
21  
20  
19  
18  
17  
16  
15  
14  
13  
3D  
4D  
V
• Center-Pin V  
and GND Pin  
Configurations Minimize High-Speed  
Switching Noise  
CC  
5
6
CC  
7
V
CC  
•
EPIC (Enhanced-Performance Implanted  
CMOS ) 1-µm Process  
8
5D  
6D  
7D  
8D  
9
• Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
10  
11  
12  
6Q  
7Q  
8Q  
CLK  
description  
The 74AC11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization  
applications in which the normal setup and hold time specifications are frequently violated.  
Synchronization of two digital signals operating at different frequencies is a common system problem. This  
problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution,  
however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the  
setup or hold time of a flip-flop is violated, the output response is uncertain. A flip-flop is metastable if its output  
hangs up in the region between V and V . The metastable condition lasts until the flip-flop recovers into one  
IL  
IH  
of its two stable states. With conventional flip-flops, this recovery time can be longer than the specified maximum  
propagation delay.  
The problem of metastability is typically solved by adding an additional layer of synchronization. This dual-rank  
approach is employed in the 74AC11478. The probability of the second stage entering the metastable state is  
exponentially reduced by this dual-rank architecture. The 74AC11478 provides a one-chip solution for system  
designers in asynchronous applications.  
The 74AC11478 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
†
CLK  
OE  
D
H
L
L
L
X
↑
↑
L
X
L
H
X
Z
L
H
Q
0
†
Data presented at the  
D inputs  
requires two clock cycles to appear at  
the Q outputs.  
EPIC is a trademark of Texas Instruments Incorporated.  
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Copyright 1993, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567

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 		AC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOIC-24
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 		Octal Dual-Rank D-Type Flip-Flops With 3-State Outputs 24-PDIP -40 to 85
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