5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> 74AC11533NT
74AC11533NT PDF预览

74AC11533NT

更新时间： 2024-11-18 04:47:27
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 129K
描述
OCTAL D-TYPE TRANSPARENY LATCHES WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

74AC11533NT 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：not_compliant风险等级：5.88
系列：ACJESD-30 代码：R-PDIP-T24
长度：31.64 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3/5 VProp。Delay @ Nom-Sup：11.4 ns
传播延迟（tpd）：10.3 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

74AC11533NT 数据手册

 浏览型号74AC11533NT的Datasheet PDF文件第2页浏览型号74AC11533NT的Datasheet PDF文件第3页浏览型号74AC11533NT的Datasheet PDF文件第4页浏览型号74AC11533NT的Datasheet PDF文件第5页浏览型号74AC11533NT的Datasheet PDF文件第6页浏览型号74AC11533NT的Datasheet PDF文件第7页 
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢄ
ꢀ
ꢅ
ꢅ
ꢆ
ꢇ
ꢈ
ꢁ
ꢂ
ꢉ ꢃꢊꢂꢋꢇꢌ ꢍꢊꢎ ꢏꢐꢇ ꢊ ꢑꢂꢒꢓꢏꢂꢑꢐ ꢒꢊ ꢇꢋꢂꢊꢃ ꢔ ꢐ  
ꢃ
ꢄ
ꢄ
ꢀ
ꢅ
ꢅ
ꢓ
ꢓ
ꢘ
ꢕ
ꢖ
ꢊ
ꢔ
ꢇ
ꢅ
ꢍ
ꢓ
ꢊ
ꢂ
ꢊ
ꢐ
ꢇ
ꢉ
ꢗ
ꢊ
ꢏ
ꢗ
ꢊ
SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993  
54AC11533 . . . JT PACKAGE  
74AC11533 . . . DW OR NT PACKAGE  
• 8-Latches in a Single Package  
• 3-State Bus-Driving Inverting Outputs  
• Full Parallel Access for Loading  
• Buffered Control Inputs  
(TOP VIEW)  
1Q  
2Q  
3Q  
OC  
1
24  
2
23 1D  
22 2D  
• Flow-Through Architecture Optimizes  
3
PCB Layout  
4
21  
20  
19  
18  
17  
16  
15  
14  
13  
4Q  
3D  
4D  
• Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
5
GND  
GND  
GND  
GND  
5Q  
6Q  
7Q  
8Q  
6
V
V
CC  
CC  
• EPICt (Enhanced-Performance Implanted  
7
CMOS) 1-mm Process  
8
5D  
6D  
7D  
8D  
C
• 500-mA Typical Latch-Up Immunity at 125°C  
9
10  
11  
12  
• Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
54AC11533 . . . FK PACKAGE  
(TOP VIEW)  
description  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
4
3
2 1 28 27 26  
5
6
7
8
9
25 7D  
24 8D  
2D  
1D  
OC  
NC  
1Q  
2Q  
3Q  
23  
22  
21  
20  
19  
C
The eight latches of the ′AC11533 are transparent  
D-type latches. While the enable (C) is high, the  
Q outputs will follow the complements of the (D)  
inputs. When the output control OC is taken low,  
the Q outputs will be latched. The ′AC11533 is  
functionally equivalent to the ′AC11373 except for  
having inverted outputs.  
NC  
8Q  
7Q  
6Q  
10  
11  
12 13 14 15 16 17 18  
A buffered output-control (OC) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or a high-  
impedance state. In the high-impedance state,  
NC − No internal connection  
the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive  
provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up  
components.  
The output control (OC) does not affect the internal operations of the latches. Old data can be retained or new  
data can be entered while the outputs are off.  
The 54AC11533 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
74AC11533 is characterized for operation from − 40°C to 85°C.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢏ
ꢏ
ꢑ
ꢉ
ꢨ
ꢌ
ꢣ
ꢗ
ꢃ
ꢡ
ꢊ
ꢢ
ꢖ
ꢜ
ꢉ
ꢚ
ꢒ
ꢛ
ꢌ
ꢂ
ꢊ
ꢂ
ꢙ
ꢚ
ꢤ
ꢛ
ꢜ
ꢢ
ꢝ
ꢞ
ꢟ
ꢟ
ꢠ
ꢠ
ꢙ
ꢙ
ꢜ
ꢜ
ꢚ
ꢚ
ꢙ
ꢡ
ꢡ
ꢥ
ꢢ
ꢣ
ꢝ
ꢝ
ꢤ
ꢤ
ꢚ
ꢠ
ꢟ
ꢞ
ꢡ
ꢡ
ꢜ
ꢛ
ꢥ
ꢊꢤ  
ꢣ
ꢦ
ꢡ
ꢧ
ꢙ
ꢢ
ꢟ
ꢡ
ꢠ
ꢙ
ꢠ
ꢜ
ꢝ
ꢚ
ꢣ
ꢨ
ꢟ
ꢚ
ꢠ
ꢠ
ꢤ
ꢡ
ꢩ
Copyright 1993, Texas Instruments Incorporated  
ꢝ
ꢜ
ꢢ
ꢠ
ꢜ
ꢝ
ꢞ
ꢠ
ꢜ
ꢡ
ꢥ
ꢙ
ꢛ
ꢙ
ꢢ
ꢤ
ꢝ
ꢠ
ꢪ
ꢠ
ꢤ
ꢝ
ꢜ
ꢛ
ꢫ
ꢟ
ꢖ
ꢚ
ꢞ
ꢤ
ꢡ
ꢠ
ꢟ
ꢚ
ꢨ
ꢟ
ꢝ
ꢨ
ꢬ
ꢟ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢝ
ꢝ
ꢟ
ꢚ
ꢠ
ꢭ
ꢩ
ꢏ
ꢝ
ꢜ
ꢨ
ꢣ
ꢢ
ꢠ
ꢙ
ꢜ
ꢚ
ꢥ
ꢝ
ꢜ
ꢢ
ꢤ
ꢡ
ꢡ
ꢙ
ꢚ
ꢮ
ꢨ
ꢜ
ꢤ
ꢡ
ꢚ
ꢜ
ꢠ
ꢚ
ꢤ
ꢢ
ꢤ
ꢡ
ꢡ
ꢟ
ꢝ
ꢙ
ꢧ
ꢭ
ꢙ
ꢚ
ꢢ
ꢧ
ꢣ
ꢨ
ꢤ
2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
12345678

中文翻译

下载PDF

与74AC11533NT相关器件

型号 品牌 获取价格 描述 数据表
74AC11534 TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
74AC11534D YAGEO

获取价格

 		Bus Driver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO24
74AC11534D-T YAGEO

获取价格

 		Bus Driver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO24
74AC11534DW TI

获取价格

 		Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs 24-SOIC -40 to 85
74AC11534DWR TI

获取价格

 		AC SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO24, PLASTIC, SO-24
74AC11534N PHILIPS

获取价格

 		D Flip-Flop, 8-Func, Positive Edge Triggered, CMOS, PDIP24
74AC11534N YAGEO

获取价格

 		Bus Driver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDIP24
74AC11534NT TI

获取价格

 		Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs 24-PDIP -40 to 85
74AC11543D PHILIPS

获取价格

 		Registered Bus Transceiver, 1-Func, 8-Bit, True Output, CMOS, PDSO28
74AC11543D YAGEO

获取价格

 		Registered Bus Transceiver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO28

与74AC11533NT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证