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74AC11521DWR PDF预览

74AC11521DWR

更新时间: 2024-11-11 13:02:55
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
5页 104K
描述
AC SERIES, 8-BIT IDENTITY COMPARATOR, INVERTED OUTPUT, PDSO20

74AC11521DWR 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.73
Is Samacsys:N其他特性:CASCADABLE
系列:ACJESD-30 代码:R-PDSO-G20
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:IDENTITY COMPARATOR位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):11.4 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

74AC11521DWR 数据手册

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www.DataSheet4U.com  
54AC11521, 74AC11521  
8-BIT IDENTITY COMPARATORS  
SCAS022A – D2957, JULY 1987 – REVISED APRIL 1993  
Compares Two 8-Bit Words  
54AC11521 . . . J PACKAGE  
74AC11521 . . . DB, DW OR N PACKAGE  
(TOP VIEW)  
Flow-Through Architecture Optimizes  
PCB Layout  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
Q1  
P1  
G
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
P2  
Q2  
P3  
Q3  
EPIC (Enhanced-Performance Implanted  
Q0  
CMOS) 1- m Process  
P0  
500-mA Typical Latch-Up Immunity at 125°C  
GND  
P = Q  
G7  
V
CC  
Package Options Include Plastic Small-  
Outline Packages, Plastic Shrink  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
P4  
Q4  
P5  
Q5  
P7  
Q6  
P6  
54AC11521 . . . FK PACKAGE  
(TOP VIEW)  
description  
These identity comparators perform comparisons  
on two 8-bit binary or BCD words. Also included  
is a P = Q totem-pole output.  
3
2
1
20 19  
18  
4
5
6
7
8
P2  
G
Q4  
P5  
Q5  
P6  
Q6  
The 54AC11521 is characterized for operation  
over the full military temperature range of – 55°C  
to 125°C. The 74AC11521 is characterized for  
operation from – 40°C to 85°C.  
17  
16  
15  
14  
Q1  
P1  
Q0  
9 10 11 12 13  
FUNCTION TABLE  
INPUTS  
OUTPUT  
P = Q  
DATA  
P, Q  
ENABLE  
G
logic symbol  
P = Q  
P > Q  
P < Q  
X
L
L
L
H
H
H
20  
G
COMP  
G1  
L
4
P0  
2
0
P
7
H
P1  
19  
P2  
17  
P3  
14  
P4  
12  
P5  
10  
P6  
8
P7  
6
1P = Q  
P = Q  
3
Q0  
1
0
Q1  
18  
Q2  
16  
Q3  
13  
Q
Q4  
11  
Q5  
9
Q6  
7
Q7  
7
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pins numbers shown are for the DW, J, and N packages.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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