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ꢔ ꢋꢌ ꢕꢍ ꢇ ꢉꢖꢌꢂꢌ ꢓꢍ ꢋꢗ ꢑꢍ ꢋꢎꢘ ꢒꢌ ꢍꢏꢓꢙ ꢋ ꢖ ꢌꢓ ꢏꢖ
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SCAS202 − MARCH 1992 − REVISED APRIL 1993
DW OR NT PACKAGE
(TOP VIEW)
• Parallel 3-State I/O: Register Inputs/
Counter Outputs
• Counter Has Direct Overriding Load and
A/Q
B/Q
C/Q
CCK
1
24
23
22
21
20
19
18
17
16
15
14
13
A
B
Clear
CCLR
2
• Flow-Through Architecture Optimizes
CCKEN
CCKEN
CLOAD
3
C
PCB Layout
D/Q
4
D
• Center-Pin V
and GND Configurations
Minimize High-Speed Switching Noise
GND
GND
GND
GND
5
CC
6
V
V
CC
CC
7
• EPICt (Enhanced-Performance Implanted
8
OE
CMOS) 1-mm Process
9
E/Q
OE
E
• 500-mA Typical Latch-Up Immunity
at 125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
10
11
12
F/Q
RCK
RCK
RCO
F
G/Q
G
H/Q
H
description
The 74AC11953 consists of a parallel input, an 8-bit storage register feeding an 8-bit counter, and a 3-state I/O
which provides parallel count outputs. Both the register and the counter have individual positive-edge triggered
clocks.
The function tables show the operation of the counter clock-enable (CCKEN, CCKEN) and output-enable (OE,
OE) inputs. A register clock-enable (RCK) input is also provided.
The counter (RCO) input has direct load and clear functions. A low-going RCO pulse will be obtained when the
counter reaches the hex word FF. Expansion is easily accomplished for two stages by connecting RCO of the
first stage to CCKEN of the second stage. Cascading for larger count chains can be accomplished by
connecting RCO of each stage to CCK of the following stage.
The 74AC11593 is characterized for operation from − 40°C to 85°C.
Function Tables
COUNTER CLOCK ENABLE
INPUTS
OUTPUT ENABLE
INPUTS
OUTPUTS
OUTPUTS
A/Q THRU H/Q
A
A/Q THRU H/Q
A H
CCKEN
CCKEN
H
OE
OE
L
L
H
H
L
H
L
Enable
Disable
Enable
Enable
L
L
H
H
L
H
L
Input mode
Input mode
Output mode
Input mode
H
H
EPIC is a trademark of Texas Instruments Incorporated.
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Copyright 1993, Texas Instruments Incorporated
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2−1
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