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71V67602S166BQG PDF预览

71V67602S166BQG

更新时间: 2024-11-19 14:46:59
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
23页 978K
描述
Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA165, 13 X 15 MM, GREEN, FBGA-165

71V67602S166BQG 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:TBGA,针数:165
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.18
Is Samacsys:N最长访问时间:3.5 ns
其他特性:PIPELINED ARCHITECTUREJESD-30 代码:R-PBGA-B165
JESD-609代码:e1长度:15 mm
内存密度:9437184 bit内存集成电路类型:CACHE SRAM
内存宽度:36功能数量:1
端子数量:165字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX36封装主体材料:PLASTIC/EPOXY
封装代码:TBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:13 mmBase Number Matches:1

71V67602S166BQG 数据手册

 浏览型号71V67602S166BQG的Datasheet PDF文件第2页浏览型号71V67602S166BQG的Datasheet PDF文件第3页浏览型号71V67602S166BQG的Datasheet PDF文件第4页浏览型号71V67602S166BQG的Datasheet PDF文件第5页浏览型号71V67602S166BQG的Datasheet PDF文件第6页浏览型号71V67602S166BQG的Datasheet PDF文件第7页 
256K X 36, 512K X 18  
3.3VSynchronousSRAMs  
2.5V I/O, Burst Counter  
IDT71V67602  
IDT71V67802  
PipelinedOutputs,SingleCycleDeselect  
Features  
Description  
256K x 36, 512K x 18 memory configurations  
Supports high system speed:  
The IDT71V67602/7802 are high-speed SRAMs organized as  
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,  
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate  
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof  
thewritecycle.  
– 166MHz 3.5ns clock access time  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V67602/7802canprovidefourcyclesof  
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
andthe LBO inputpin.  
TheIDT71V67602/7802SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
(1 )  
BW1, BW2, BW3, BW4  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
VDD, VDDQ  
VSS  
Supply  
Supply  
N/A  
5311 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V67802.  
DECEMBER 2003  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5311/07  

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