Datasheet > 71V67602S166BQG8

71V67602S166BQG8

更新时间： 2024-11-09 08:46:39

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
23页	517K
描述
SRAM

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中文翻译

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数据手册

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71V67602S166BQG8 数据手册

256K X 36, 512K X 18

3.3VSynchronousSRAMs

2.5V I/O, Burst Counter

IDT71V67602

IDT71V67802

PipelinedOutputs,SingleCycleDeselect

Features

Description

◆

256K x 36, 512K x 18 memory configurations

Supports high system speed:

The IDT71V67602/7802 are high-speed SRAMs organized as

256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

◆

LBO input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O supply (VDDQ)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array.

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V67602/7802canprovidefourcyclesof

dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

orderofthesethreeaddressesaredefinedbytheinternalburstcounter

andthe LBO inputpin.

◆

TheIDT71V67602/7802SRAMsutilizeIDT’slatesthigh-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

A⁰-A¹⁸

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CS⁰, CS1

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

(1 )

BW¹, BW², BW³, BW4

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O⁰-I/O³¹, I/O^P1-I/O^P4

Data Input / Output

Core Power, I/O Power

Ground

V^DD, V^DDQ

V^SS

Supply

N/A

5311 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V67802.

FEBRUARY 2009

DECEMBER 2003

DSC-5311/07

12 3 4 5 6 7...23

中文翻译

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与71V67602S166BQG8相关器件

型号	品牌	获取价格	描述	数据表
71V67602S166BQGI8	IDT	获取价格	SRAM
71V67602S166BQI8	IDT	获取价格	SRAM
71V67602S166PF	IDT	获取价格	Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ,
71V67602S166PFG8	IDT	获取价格	TQFP-100, Reel
71V67603	RENESAS	获取价格	3.3V 256K x 36 Synchronous 3.3V I/O PipeLined SRAM
71V67603S133BG8	IDT	获取价格	PBGA-119, Reel
71V67603S133BGG8	IDT	获取价格	PBGA-119, Reel
71V67603S133BGGI8	IDT	获取价格	PBGA-119, Reel
71V67603S133BGI8	IDT	获取价格	PBGA-119, Reel
71V67603S133BQ8	IDT	获取价格	CABGA-165, Reel

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