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71V67602S166BQG8 PDF预览

71V67602S166BQG8

更新时间: 2024-11-20 08:46:39
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
23页 517K
描述
SRAM

71V67602S166BQG8 数据手册

 浏览型号71V67602S166BQG8的Datasheet PDF文件第2页浏览型号71V67602S166BQG8的Datasheet PDF文件第3页浏览型号71V67602S166BQG8的Datasheet PDF文件第4页浏览型号71V67602S166BQG8的Datasheet PDF文件第5页浏览型号71V67602S166BQG8的Datasheet PDF文件第6页浏览型号71V67602S166BQG8的Datasheet PDF文件第7页 
256K X 36, 512K X 18  
3.3VSynchronousSRAMs  
2.5V I/O, Burst Counter  
IDT71V67602  
IDT71V67802  
PipelinedOutputs,SingleCycleDeselect  
Features  
Description  
256K x 36, 512K x 18 memory configurations  
Supports high system speed:  
The IDT71V67602/7802 are high-speed SRAMs organized as  
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,  
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate  
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof  
thewritecycle.  
– 166MHz 3.5ns clock access time  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V67602/7802canprovidefourcyclesof  
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
andthe LBO inputpin.  
TheIDT71V67602/7802SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
(1 )  
BW1, BW2, BW3, BW4  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
VDD, VDDQ  
VSS  
Supply  
Supply  
N/A  
5311 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V67802.  
FEBRUARY 2009  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5311/07  

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