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71V67603 PDF预览

71V67603

更新时间: 2024-11-20 14:57:51
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器
页数 文件大小 规格书
23页 297K
描述
3.3V 256K x 36 Synchronous 3.3V I/O PipeLined SRAM

71V67603 数据手册

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256K X 36, 512K X 18  
3.3VSynchronousSRAMs  
3.3V I/O, Burst Counter  
71V67603  
71V67803  
PipelinedOutputs,SingleCycleDeselect  
Features  
256K x 36, 512K x 18 memory configurations  
Supports high system speed:  
LBO input selects interleaved or linear burst mode  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin thin plastic quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA).  
– 166MHz 3.5ns clock access time  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
FunctionalBlockDiagram  
LBO  
ADV  
INTERNAL  
ADDRESS  
CEN  
256K x 36/  
512K x 18-  
BIT  
MEMORY  
ARRAY  
CLK  
2
Burst  
Logic  
18/19  
Binary  
Counter  
ADSC  
A0*  
A1*  
Q0  
Q1  
CLR  
ADSP  
2
CLK EN  
A0,A1  
A2–A18  
A0–A17/18  
ADDRESS  
REGISTER  
36/18  
36/18  
18/19  
GW  
Byte 1  
Write Register  
BWE  
Byte 1  
Write Driver  
BW  
1
9
9
Byte 2  
Write Register  
Byte 2  
Write Driver  
BW2  
Byte 3  
Write Register  
Byte 3  
Write Driver  
BW  
3
9
9
Byte 4  
Write Register  
Byte 4  
Write Driver  
BW4  
OUTPUT  
REGISTER  
CE  
CS  
CS  
Q
D
0
Enable  
DATA INPUT  
REGISTER  
1
Register  
CLK EN  
ZZ  
Powerdown  
D
Q
Enable  
Delay  
Register  
OE  
OUTPUT  
BUFFER  
OE  
,
36/18  
I/O  
0
–I/O31  
I/OP1–I/OP4  
5301 drw 01  
1
Sep.13.21  

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