PRELIMINARY
IDT70P256/246L
VERY LOW POWER 1.8V
8K/4K x 16 DUAL-PORT
STATIC RAM
Features
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◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
Input Read Register
◆
◆
◆
◆
Output Drive Register
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
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◆
– Industrial:55ns (max.)
Low-power operation
IDT70P256/246L
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◆
◆
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◆
Active:27mW(typ.)
Standby:3.6µW(typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
Supports 3.0V and 2.5V I/O's
Fully asynchronous operation from either port
LVTTL-compatible, single 1.8V (±100mV) power supply
Available in 100 Ball 0.5mm-pitch BGA
Industrial temperature range (-40°C to +85°C)
Green parts available, see ordering information
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Functional Block Diagram
R/W
R
R/W
UB
L
L
UB
R
LB
CE
OE
R
LB
CE
OE
L
L
L
R
R
,
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0R-I/O7R
BUSY (2)
L
(2)
BUSY
R
(1)
(1)
A
A
12R
0R
A
12L
Address
Decoder
Address
Decoder
MEMORY
ARRAY
A
0L
CE
OE
R/W
IRR
L
CE
OE
R/W
ODR
R
INPUT
READ REGISTER
AND
L
R
L
R
OUTPUT
DRIVE REGISTER
ODR
0
-
4
0,IRR1
SFEN
13
13
CE
L
CE
R
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
L
OE
R
R/W
L
R/W
R
SEM
L
SEM
R
(2)
INT (2)
L
INT
R
5699 drw 01
NOTES:
1. A12X is a NC for IDT70P246.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
JANUARY 2009
1
DSC-5699/2
©2009IntegratedDeviceTechnology,Inc.